Naresh R. Shanbhag
Orcid: 0000-0002-4323-9164Affiliations:
- University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, IL, USA
According to our database1,
Naresh R. Shanbhag
authored at least 234 papers
between 1991 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2006, "For development of a communication-centric design paradigm for low power systems on a chip.".
Timeline
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Bibliography
2023
Proceedings of the International Conference on Machine Learning, 2023
Enhancing the Accuracy of Resistive In-Memory Architectures using Adaptive Signal Processing.
Proceedings of the IEEE International Conference on Acoustics, 2023
Boosting the Accuracy of SRAM-Based in-Memory Architectures Via Maximum Likelihood-Based Error Compensation Method.
Proceedings of the IEEE International Conference on Acoustics, 2023
Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Fundamental Limits on Energy-Delay-Accuracy of In-Memory Architectures in Inference Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
CoRR, 2022
Fundamental Limits on the Computational Accuracy of Resistive Crossbar-based In-memory Architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the International Conference on Machine Learning, 2022
Proceedings of the IEEE International Conference on Acoustics, 2022
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures.
IEEE Trans. Signal Process., 2021
A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting.
IEEE J. Solid State Circuits, 2021
CoRR, 2021
Generalized Depthwise-Separable Convolutions for Adversarially Robust and Efficient Neural Networks.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Proceedings of the 32nd IEEE International Symposium on Software Reliability Engineering, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
Deep In-Memory Architectures for Machine Learning-Accuracy Versus Efficiency Trade-Offs.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Proc. IEEE, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Low-Complexity Fixed-Point Convolutional Neural Networks For Automatic Target Recognition.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the Computer Vision - ECCV 2020, 2020
KeyRAM: A 0.34 uJ/decision 18 k decisions/s Recurrent Attention In-memory Processor for Keyword Spotting.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
An Energy-Efficient Programmable Mixed-Signal Accelerator for Machine Learning Algorithms.
IEEE Micro, 2019
IEEE Commun. Lett., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 7th International Conference on Learning Representations, 2019
Proceedings of the 7th International Conference on Learning Representations, 2019
2018
A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage Regime.
J. Signal Process. Syst., 2018
IEEE Trans. Commun., 2018
IEEE J. Solid State Circuits, 2018
A 19.4-nJ/Decision, 364-K Decisions/s, In-Memory Random Forest Multi-Class Inference Accelerator.
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Symposium on Information Theory, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
An Analytical Method to Determine Minimum Per-Layer Precision of Deep Neural Networks.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
True Gradient-Based Training of Deep Binary Activated Neural Networks Via Continuous Binarization.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
IEEE Trans. Commun., 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 34th International Conference on Machine Learning, 2017
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Embedded Algorithmic Noise-Tolerance for Signal Processing and Machine Learning Systems via Data Path Decomposition.
IEEE Trans. Signal Process., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Biomed. Circuits Syst., 2016
Correction to "An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation".
IEEE J. Solid State Circuits, 2016
CoRR, 2016
CoRR, 2016
CoRR, 2016
A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array.
CoRR, 2016
Variation-Tolerant Architectures for Convolutional Neural Networks in the Near Threshold Voltage Regime.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
2014
Reducing Energy at the Minimum Energy Operating Point Via Statistical Error Compensation.
IEEE Trans. Very Large Scale Integr. Syst., 2014
System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-V<sub>t</sub> Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS.
IEEE J. Solid State Circuits, 2014
Energy-efficient dot product computation using a switched analog circuit architecture.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Space-time slicer architectures for analog-to-information conversion in channel equalizers.
Proceedings of the IEEE International Conference on Communications, 2014
An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM.
Proceedings of the IEEE International Conference on Acoustics, 2014
A robust message passing based stereo matching kernel via system-level error resiliency.
Proceedings of the IEEE International Conference on Acoustics, 2014
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
Energy-efficient accelerator architecture for stereo image matching using approximate computing and statistical error compensation.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
IEEE Trans. Multim., 2013
An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation.
IEEE J. Solid State Circuits, 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
2012
IEEE Trans. Signal Process., 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
IEEE Trans. Inf. Theory, 2011
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
System energy minimization via joint optimization of the DC-DC converter and the core.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Least squares approximation and polyphase decomposition for pipelining recursive filters.
Proceedings of the IEEE International Conference on Acoustics, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Low power and error resilient PN code acquisition filter via statistical error compensation.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Computation as estimation: a general framework for robustness and energy efficiency in SoCs.
IEEE Trans. Signal Process., 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the IEEE International Conference on Acoustics, 2010
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
IEEE Trans. Signal Process., 2009
Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE J. Solid State Circuits, 2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 10Gb/s MLSE-based Electronic-Dispersion-Compensation IC with Fast Power-Transient Management for WDM Add/Drop Networks.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption.
Proceedings of the IEEE International Conference on Acoustics, 2008
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
2007
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the International Symposium on System-on-Chip, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2005
A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes.
J. VLSI Signal Process., 2005
J. VLSI Signal Process., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Signal Process., 2005
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew.
IEEE J. Solid State Circuits, 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Complexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber line.
IEEE Trans. Signal Process., 2003
IEEE Trans. Signal Process., 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the Global Telecommunications Conference, 2003
2002
IEEE J. Solid State Circuits, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the IEEE International Conference on Acoustics, 2002
Proceedings of the Global Telecommunications Conference, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
J. VLSI Signal Process., 2001
J. VLSI Signal Process., 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE J. Solid State Circuits, 2001
Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Low-power decimation filters for oversampling ADCs via the decorrelating (DECOR) transform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Algorithmic noise-tolerance for low-power signal processing in the deep submicron era.
Proceedings of the 10th European Signal Processing Conference, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing.
IEEE Trans. Very Large Scale Integr. Syst., 1999
A low-power phase-splitting adaptive equalizer for high bit-rate communication systems.
IEEE Trans. Signal Process., 1999
IEEE Trans. Signal Process., 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the Third IEEE Workshop on Multimedia Signal Processing, 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
1998
IEEE Trans. Signal Process., 1998
IEEE Trans. Signal Process., 1998
Int. J. Wirel. Inf. Networks, 1998
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
Proceedings of the Second IEEE Workshop on Multimedia Signal Processing, 1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT).
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
1997
IEEE Trans. Signal Process., 1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the 34st Conference on Design Automation, 1997
1996
Pipelined adaptive IIR filter architectures using scattered and relaxed look-ahead transformations.
IEEE Trans. Signal Process., 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1995
IEEE Trans. Signal Process., 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1993
A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Roundoff error analysis of the pipelined ADPCM coder.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
1991
IEEE Trans. Signal Process., 1991