Naresh R. Shanbhag
According to our database^{1},
Naresh R. Shanbhag
authored at least 208 papers
between 1991 and 2020.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2006, "For development of a communicationcentric design paradigm for low power systems on a chip.".
Timeline
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on orcid.org
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Bibliography
2020
Deep InMemory Architectures for Machine LearningAccuracy Versus Efficiency TradeOffs.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Deep InMemory Architectures in SRAM: An Analog Approach to Approximate Computing.
Proc. IEEE, 2020
Fundamental Limits on EnergyDelayAccuracy of Inmemory Architectures in Inference Applications.
CoRR, 2020
CoRR, 2020
CoRR, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
LowComplexity FixedPoint Convolutional Neural Networks For Automatic Target Recognition.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the Computer Vision  ECCV 2020, 2020
KeyRAM: A 0.34 uJ/decision 18 k decisions/s Recurrent Attention Inmemory Processor for Keyword Spotting.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Proc. IEEE, 2019
An EnergyEfficient Programmable MixedSignal Accelerator for Machine Learning Algorithms.
IEEE Micro, 2019
IEEE Commun. Lett., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 7th International Conference on Learning Representations, 2019
Proceedings of the 7th International Conference on Learning Representations, 2019
2018
A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage Regime.
J. Signal Process. Syst., 2018
IEEE Trans. Commun., 2018
IEEE J. Solid State Circuits, 2018
A 19.4nJ/Decision, 364K Decisions/s, InMemory Random Forest MultiClass Inference Accelerator.
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
A 42pJ/decision 3.12TOPS/W robust inmemory machine learning classifier with onchip training.
Proceedings of the 2018 IEEE International SolidState Circuits Conference, 2018
Proceedings of the 2018 IEEE International Symposium on Information Theory, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
PROMISE: An EndtoEnd Design of a Programmable MixedSignal Accelerator for MachineLearning Algorithms.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
An Analytical Method to Determine Minimum PerLayer Precision of Deep Neural Networks.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
True GradientBased Training of Deep Binary Activated Neural Networks Via Continuous Binarization.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
IEEE Trans. Commun., 2017
CoRR, 2017
PredictiveNet: An energyefficient convolutional neural network via zero prediction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 34th International Conference on Machine Learning, 2017
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
A 19.4 nJ/decision 364K decisions/s inmemory random forest classifier in 6T SRAM array.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Embedded Algorithmic NoiseTolerance for Signal Processing and Machine Learning Systems via Data Path Decomposition.
IEEE Trans. Signal Process., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Biomed. Circuits Syst., 2016
Correction to "An EnergyEfficient ECG Processor in 45nm CMOS Using Statistical Error Compensation".
IEEE J. Solid State Circuits, 2016
ErrorResilient Machine Learning in Near Threshold Voltage via Classifier Ensemble.
CoRR, 2016
CoRR, 2016
CoRR, 2016
CoRR, 2016
A 481pJ/decision 3.4M decision/s Multifunctional Deep Inmemory Inference Processor using Standard 6T SRAM Array.
CoRR, 2016
VariationTolerant Architectures for Convolutional Neural Networks in the Near Threshold Voltage Regime.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
A 3.6mW 50MHz PN Code Acquisition Filter via Statistical Error Compensation in 180nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels.
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 2015
An energyefficient memorybased highthroughput VLSI architecture for convolutional networks.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
2014
Reducing Energy at the Minimum Energy Operating Point Via Statistical Error Compensation.
IEEE Trans. Very Large Scale Integr. Syst., 2014
SystemLevel Optimization of SwitchedCapacitor VRM and Core for Sub/NearV<sub>t</sub> Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 0.79 pJ/KGate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/NearThreshold Operation in 130 nm CMOS.
IEEE J. Solid State Circuits, 2014
Energyefficient dot product computation using a switched analog circuit architecture.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Spacetime slicer architectures for analogtoinformation conversion in channel equalizers.
Proceedings of the IEEE International Conference on Communications, 2014
An energyefficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM.
Proceedings of the IEEE International Conference on Acoustics, 2014
A robust message passing based stereo matching kernel via systemlevel error resiliency.
Proceedings of the IEEE International Conference on Acoustics, 2014
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
Energyefficient accelerator architecture for stereo image matching using approximate computing and statistical error compensation.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
IEEE Trans. Multim., 2013
An EnergyEfficient ECG Processor in 45nm CMOS Using Statistical Error Compensation.
IEEE J. Solid State Circuits, 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
2012
IEEE Trans. Signal Process., 2012
IEEE Trans. Computers, 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Systemdriven metrics for the design and adaptation of analog to digital converters.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
A fully automated technique for constructing FSM abstractions of nonideal latches in communication systems.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
A 14.5 fJ/cycle/kgate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
IEEE Trans. Inf. Theory, 2011
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
System energy minimization via joint optimization of the DCDC converter and the core.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Least squares approximation and polyphase decomposition for pipelining recursive filters.
Proceedings of the IEEE International Conference on Acoustics, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Low power and error resilient PN code acquisition filter via statistical error compensation.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Computation as estimation: a general framework for robustness and energy efficiency in SoCs.
IEEE Trans. Signal Process., 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Embed. Syst. Lett., 2010
Proceedings of the IEEE International SolidState Circuits Conference, 2010
Proceedings of the IEEE International SolidState Circuits Conference, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the IEEE International Conference on Acoustics, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
IEEE Trans. Signal Process., 2009
Lowpower implementation of a highthroughput LDPC decoder for IEEE 802.11N standard.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the 2008 IEEE International Symposium on SystemonChip, 2009
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Signal Process. Mag., 2008
IEEE J. Solid State Circuits, 2008
IEEE Des. Test Comput., 2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Proceedings of the 2008 IEEE International SolidState Circuits Conference, 2008
A 10Gb/s MLSEbased ElectronicDispersionCompensation IC with Fast PowerTransient Management for WDM Add/Drop Networks.
Proceedings of the 2008 IEEE International SolidState Circuits Conference, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Computation as estimation: Estimationtheoretic IC design improves robustness and reduces power consumption.
Proceedings of the IEEE International Conference on Acoustics, 2008
Trends in energyefficiency and robustness using stochastic sensor networkonachip.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Coding for Reliable OnChip Buses: A Class of Fundamental Bounds and Practical Codes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the International Symposium on SystemonChip, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2005
J. VLSI Signal Process., 2005
A Novel Design Methodology for HighPerformance Programmable Decoder Cores for AALDPC Codes.
J. VLSI Signal Process., 2005
J. VLSI Signal Process., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Signal Process., 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Reliable lowpower digital signal processing via reduced precision redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2004
Computer, 2004
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Energyefficiency bounds for deep submicron VLSI systems in the presence of noise.
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Complexity analysis of multicarrier and singlecarrier systems for very highspeed digital subscriber line.
IEEE Trans. Signal Process., 2003
IEEE Trans. Signal Process., 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the Global Telecommunications Conference, 2003
2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the IEEE International Conference on Acoustics, 2002
Proceedings of the Global Telecommunications Conference, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
J. VLSI Signal Process., 2001
J. VLSI Signal Process., 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
Lowpower AECbased MIMO signal processing for gigabit ethernet 1000BaseT transceivers.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Reliable lowpower design in the presence of deep submicron noise (embedded tutorial session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Lowpower decimation filters for oversampling ADCs via the decorrelating (DECOR) transform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Proceedings of the 2000 IEEE/ACM International Conference on ComputerAided Design, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Algorithmic noisetolerance for lowpower signal processing in the deep submicron era.
Proceedings of the 10th European Signal Processing Conference, 2000
1999
Informationtheoretic bounds on average signal transition activity [VLSI systems].
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
Dynamic algorithm transformations (DAT)a systematic approach to lowpower reconfigurable signal processing.
IEEE Trans. Very Large Scale Integr. Syst., 1999
A lowpower phasesplitting adaptive equalizer for high bitrate communication systems.
IEEE Trans. Signal Process., 1999
IEEE Trans. Signal Process., 1999
Analytical Expressions for Power Dissipation of Macroblocks in DSP Architectures.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the Third IEEE Workshop on Multimedia Signal Processing, 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Lowpower distributed arithmetic architectures using nonuniform memory partitioning.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
1998
IEEE Trans. Signal Process., 1998
IEEE Trans. Signal Process., 1998
IEEE Trans. Signal Process., 1998
Int. J. Wirel. Inf. Networks, 1998
Coding for LowPower Address and Data Busses: A SourceCoding Framework and Applications.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
Proceedings of the Second IEEE Workshop on Multimedia Signal Processing, 1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 1998 IEEE/ACM International Conference on ComputerAided Design, 1998
Lowpower reconfigurable signal processing via dynamic algorithm transformations (DAT).
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
1997
Lowpower adaptive filter architectures and their application to 51.84 Mb/s ATMLAN.
IEEE Trans. Signal Process., 1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Proceedings of the 1997 IEEE/ACM International Conference on ComputerAided Design, 1997
Proceedings of the 34st Conference on Design Automation, 1997
1996
Pipelined adaptive IIR filter architectures using scattered and relaxed lookahead transformations.
IEEE Trans. Signal Process., 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1995
IEEE Trans. Signal Process., 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1993
IEEE Trans. Signal Process., 1993
A Pipelined Adaptive Differential Vector Quantizer for Lowpower Speech Coding Applications.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Roundoff error analysis of the pipelined ADPCM coder.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
1991
IEEE Trans. Signal Process., 1991