Naresh R. Shanbhag

According to our database1, Naresh R. Shanbhag authored at least 186 papers between 1991 and 2019.

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Awards

IEEE Fellow

IEEE Fellow 2006, "For development of a communication-centric design paradigm for low power systems on a chip.".

Timeline

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Bibliography

2019
Shannon-Inspired Statistical Computing for the Nanoscale Era.
Proceedings of the IEEE, 2019

Efficient Local Secret Sharing for Distributed Blockchain Systems.
IEEE Communications Letters, 2019

Minimum Precision Requirements of General Margin Hyperplane Classifiers.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

An Energy-Efficient Classifier via Boosted Spin Channel Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks.
Proceedings of the 7th International Conference on Learning Representations, 2019

Per-Tensor Fixed-Point Quantization of the Back-Propagation Algorithm.
Proceedings of the 7th International Conference on Learning Representations, 2019

2018
A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage Regime.
Signal Processing Systems, 2018

Generalized Water-Filling for Source-Aware Energy-Efficient SRAMs.
IEEE Trans. Communications, 2018

A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array.
J. Solid-State Circuits, 2018

A 19.4-nJ/Decision, 364-K Decisions/s, In-Memory Random Forest Multi-Class Inference Accelerator.
J. Solid-State Circuits, 2018

A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training.
J. Solid-State Circuits, 2018

An In-Memory VLSI Architecture for Convolutional Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

SRAM Bit-line Swings Optimization using Generalized Waterfilling.
Proceedings of the 2018 IEEE International Symposium on Information Theory, 2018

Energy-Efficient Deep In-memory Architecture for NAND Flash Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

An Analytical Method to Determine Minimum Per-Layer Precision of Deep Neural Networks.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

True Gradient-Based Training of Deep Binary Activated Neural Networks Via Continuous Binarization.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Minimum Precision Requirements for Deep Learning with Biomedical Datasets.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017
Slicer Architectures for Analog-to-Information Conversion in Channel Equalizers.
IEEE Trans. Communications, 2017

PredictiveNet: An energy-efficient convolutional neural network via zero prediction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Analytical Guarantees on Numerical Precision of Deep Neural Networks.
Proceedings of the 34th International Conference on Machine Learning, 2017

Minimum precision requirements for the SVM-SGD learning algorithm.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A Systems Approach to Computing in Beyond CMOS Fabrics: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching.
IEEE Trans. VLSI Syst., 2016

Embedded Algorithmic Noise-Tolerance for Signal Processing and Machine Learning Systems via Data Path Decomposition.
IEEE Trans. Signal Processing, 2016

A Study of BER-Optimal ADC-Based Receiver for Serial Links.
IEEE Trans. on Circuits and Systems, 2016

In-Memory Computing Architectures for Sparse Distributed Memory.
IEEE Trans. Biomed. Circuits and Systems, 2016

Correction to "An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation".
J. Solid-State Circuits, 2016

Variation-Tolerant Architectures for Convolutional Neural Networks in the Near Threshold Voltage Regime.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Perfect error compensation via algorithmic error cancellation.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Analysis of error resiliency of belief propagation in computer vision.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS.
IEEE Trans. VLSI Syst., 2015

Statistical information processing: Computing for the nanoscale era.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Energy-efficient and high throughput sparse distributed memory architecture.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

2014
Reducing Energy at the Minimum Energy Operating Point Via Statistical Error Compensation.
IEEE Trans. VLSI Syst., 2014

System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-Vt Computing.
IEEE Trans. on Circuits and Systems, 2014

A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS.
J. Solid-State Circuits, 2014

Energy-efficient dot product computation using a switched analog circuit architecture.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Space-time slicer architectures for analog-to-information conversion in channel equalizers.
Proceedings of the IEEE International Conference on Communications, 2014

An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM.
Proceedings of the IEEE International Conference on Acoustics, 2014

A robust message passing based stereo matching kernel via system-level error resiliency.
Proceedings of the IEEE International Conference on Acoustics, 2014

Embedded error compensation for energy efficient DSP systems.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

Energy-efficient accelerator architecture for stereo image matching using approximate computing and statistical error compensation.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

2013
Signal Processing for High-Speed Links.
Proceedings of the Handbook of Signal Processing Systems, 2013

Robust and Energy Efficient Multimedia Systems via Likelihood Processing.
IEEE Trans. Multimedia, 2013

An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation.
J. Solid-State Circuits, 2013

Error resilient MRF message passing architecture for stereo matching.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Error-resilient systems via statistical signal processing.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Statistical analysis of algorithmic noise tolerance.
Proceedings of the IEEE International Conference on Acoustics, 2013

2012
BER-Optimal Analog-to-Digital Converters for Communication Links.
IEEE Trans. Signal Processing, 2012

Soft N-Modular Redundancy.
IEEE Trans. Computers, 2012

Energy-Efficient LDPC Decoders Based on Error-Resiliency.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

System-driven metrics for the design and adaptation of analog to digital converters.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

FEC-based 4 Gb/s backplane transceiver in 90nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A sphere decoding approach for the vector Viterbi algorithm.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
An energy-efficient multiple-input multiple-output (MIMO) detector architecture.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

System energy minimization via joint optimization of the DC-DC converter and the core.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Least squares approximation and polyphase decomposition for pipelining recursive filters.
Proceedings of the IEEE International Conference on Acoustics, 2011

System-assisted analog mixed-signal design.
Proceedings of the Design, Automation and Test in Europe, 2011

Timing error statistics for energy-efficient robust DSP systems.
Proceedings of the Design, Automation and Test in Europe, 2011

Low power and error resilient PN code acquisition filter via statistical error compensation.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Stochastic Networked Computation.
IEEE Trans. VLSI Syst., 2010

Computation as estimation: a general framework for robustness and energy efficiency in SoCs.
IEEE Trans. Signal Processing, 2010

Design of Energy-Efficient High-Speed Links via Forward Error Correction.
IEEE Trans. on Circuits and Systems, 2010

Minimum-Energy Operation Via Error Resiliency.
Embedded Systems Letters, 2010

Energy-efficient high-speed interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Transceiver circuits for optical communications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

BER-optimal analog-to-digital converters for communication links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Robust and energy-efficient DSP systems via output probability processing.
Proceedings of the 28th International Conference on Computer Design, 2010

Soft NMR: Analysis & application to DSP systems.
Proceedings of the IEEE International Conference on Acoustics, 2010

Stochastic computation.
Proceedings of the 47th Design Automation Conference, 2010

Signal Processing for High-Speed Links.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Error-resilient low-power Viterbi decoder architectures.
IEEE Trans. Signal Processing, 2009

Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

2008
Error-Resilient Motion Estimation Architecture.
IEEE Trans. VLSI Syst., 2008

Joint Equalization and Coding for On-Chip Bus Communication.
IEEE Trans. VLSI Syst., 2008

Fast Power Transient Management for OC-192 WDM Add/Drop Networks.
J. Solid-State Circuits, 2008

The Search for Alternative Computational Paradigms.
IEEE Design & Test of Computers, 2008

Error-resilient low-power Viterbi decoders via state clustering.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Trends and Challenges in Optical Communications Front-End.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 10Gb/s MLSE-based Electronic-Dispersion-Compensation IC with Fast Power-Transient Management for WDM Add/Drop Networks.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Error-resilient low-power Viterbi decoders.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption.
Proceedings of the IEEE International Conference on Acoustics, 2008

Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Variation-Tolerant Motion Estimation Architecture.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

2006
Sequential Element Design With Built-In Soft Error Resilience.
IEEE Trans. VLSI Syst., 2006

Energy-efficient soft error-tolerant digital signal processing.
IEEE Trans. VLSI Syst., 2006

Dual-Sampling Skewed CMOS Design for Soft-Error Tolerance.
IEEE Trans. on Circuits and Systems, 2006

Soft-Error-Rate-Analysis (SERA) Methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Energy-efficient motion estimation using error-tolerance.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005
Guest Editorial.
VLSI Signal Processing, 2005

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes.
VLSI Signal Processing, 2005

Energy Efficient VLSI Architecture for Linear Turbo Equalizer.
VLSI Signal Processing, 2005

Area-efficient high-throughput MAP decoder architectures.
IEEE Trans. VLSI Syst., 2005

Linear turbo equalization analysis via BER transfer and EXIT charts.
IEEE Trans. Signal Processing, 2005

Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Joint Equalization and Coding for On-Chip Bus Communication.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A low-power bus design using joint repeater insertion and coding.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

An energy-efficient circuit technique for single event transient noise-tolerance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Reliable low-power digital signal processing via reduced precision redundancy.
IEEE Trans. VLSI Syst., 2004

Reliable and Efficient System-on-Chip Design.
IEEE Computer, 2004

Reduced complexity interpolation for soft-decoding of reed-solomon codes.
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004

Switching methods for linear turbo equalization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A soft error rate analysis (SERA) methodology.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

VLSI architectures for soft-decision decoding of Reed-Solomon codes.
Proceedings of IEEE International Conference on Communications, 2004

Switching LMS linear turbo equalization.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Coding for system-on-chip networks: a unified framework.
Proceedings of the 41th Design Automation Conference, 2004

A communication-theoretic design paradigm for reliable SOCs.
Proceedings of the 41th Design Automation Conference, 2004

2003
Low-power MIMO signal processing.
IEEE Trans. VLSI Syst., 2003

Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise.
IEEE Trans. VLSI Syst., 2003

High-throughput LDPC decoders.
IEEE Trans. VLSI Syst., 2003

VLSI architectures for SISO-APP decoders.
IEEE Trans. VLSI Syst., 2003

Complexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber line.
IEEE Trans. Signal Processing, 2003

Low-power filtering via adaptive error-cancellation.
IEEE Trans. Signal Processing, 2003

A low-power VLSI architecture for turbo decoding.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Performance analysis of algorithmic noise-tolerance techniques.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Architecture-aware low-density parity-check codes.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

High bandwidth transimpedance amplifier design using active transmission lines.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Analysis of linear turbo equalizer via EXIT chart.
Proceedings of the Global Telecommunications Conference, 2003

2002
Low-power VLSI decoder architectures for LDPC codes.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Simplified current and delay models for deep submicron CMOS digital circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Design methodology for high-speed iterative decoder architectures.
Proceedings of the IEEE International Conference on Acoustics, 2002

Turbo decoder architectures for low-density parity-check codes.
Proceedings of the Global Telecommunications Conference, 2002

Reliable and energy-efficient digital signal processing.
Proceedings of the 39th Design Automation Conference, 2002

2001
Guest Editorial: Reconfigurable Signal Processing Systems.
VLSI Signal Processing, 2001

Total System Energy Minimization for Wireless Image Transmission.
VLSI Signal Processing, 2001

High-speed architectures for Reed-Solomon decoders.
IEEE Trans. VLSI Syst., 2001

Soft digital signal processing.
IEEE Trans. VLSI Syst., 2001

Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Toward achieving energy efficiency in presence of deep submicron noise.
IEEE Trans. VLSI Syst., 2000

Reliable low-power design in the presence of deep submicron noise (embedded tutorial session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Architecture driven filter transformations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Low-power digital filtering via soft DSP.
Proceedings of the IEEE International Conference on Acoustics, 2000

Algorithmic noise-tolerance for low-power signal processing in the deep submicron era.
Proceedings of the 10th European Signal Processing Conference, 2000

1999
Information-theoretic bounds on average signal transition activity [VLSI systems].
IEEE Trans. VLSI Syst., 1999

A coding framework for low-power address and data busses.
IEEE Trans. VLSI Syst., 1999

Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing.
IEEE Trans. VLSI Syst., 1999

A low-power phase-splitting adaptive equalizer for high bit-rate communication systems.
IEEE Trans. Signal Processing, 1999

Dynamic algorithm transforms for low-power reconfigurable adaptive equalizers.
IEEE Trans. Signal Processing, 1999

Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A low power data-adaptive motion estimation algorithm.
Proceedings of the Third IEEE Workshop on Multimedia Signal Processing, 1999

Energy-efficient signal processing via algorithmic noise-tolerance.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Energy-efficient dynamic circuit design in the presence of crosstalk noise.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Noise-tolerant dynamic circuit design.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low-power distributed arithmetic architectures using nonuniform memory partitioning.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low-power channel coding via dynamic reconfiguration.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1998
VLSI systems design of 51.84 Mb/s transceivers for ATM-LAN and broadband access.
IEEE Trans. Signal Processing, 1998

A pipelined adaptive NEXT canceller.
IEEE Trans. Signal Processing, 1998

Finite-precision analysis of the pipelined strength-reduced adaptive filter.
IEEE Trans. Signal Processing, 1998

Algorithms Transformation Techniques for Low-Power Wireless VLSI Systems Design.
IJWIN, 1998

Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Efficient wireless image transmission under a total power constraint.
Proceedings of the Second IEEE Workshop on Multimedia Signal Processing, 1998

Decorrelating (DECOR) transformations for low-power adaptive filters.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Energy-efficiency in presence of deep submicron noise.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT).
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Improving the throughput of flexible-precision DSPS via algorithm transformation.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997
Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN.
IEEE Trans. Signal Processing, 1997

Analytical estimation of signal transition activity from word-level statistics.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Dynamic algorithm transformation (DAT) for low-power adaptive signal processing.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Achievable bounds on signal transition activity.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Analytical Estimation of Transition Activity From Word-Level Signal Statistics.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Pipelined adaptive IIR filter architectures using scattered and relaxed look-ahead transformations.
IEEE Trans. Signal Processing, 1996

Lower bounds on power dissipation for DSP algorithms.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Low-power adaptive filter architectures via strength reduction.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
Pipelined adaptive DFE architectures using relaxed look-ahead.
IEEE Trans. Signal Processing, 1995

Pipelined Adaptive IIR Filter Architecture.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1993
A pipelined adaptive lattice filter architecture.
IEEE Trans. Signal Processing, 1993

A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Roundoff error analysis of the pipelined ADPCM coder.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1991
An improved systolic architecture for 2-D digital filters.
IEEE Trans. Signal Processing, 1991


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