Caleb Serafy

According to our database1, Caleb Serafy authored at least 16 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2017
TSV-Based 3-D ICs: Design Methods and Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Design Space Modeling and Simulation for Physically Constrained 3D CPUs.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Unlocking the True Potential of 3-D CPUs With Microfluidic Cooling.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Security and Vulnerability Implications of 3D ICs.
IEEE Trans. Multi Scale Comput. Syst., 2016

Thermoelectric Codesign of 3-D CPUs and Embedded Microfluidic Pin-Fin Heatsinks.
IEEE Des. Test, 2016

Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
TSV Replacement and Shield Insertion for TSV-TSV Coupling Reduction in 3-D Global Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014
A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs.
Integr., 2014

Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts.
Proceedings of the International Symposium on Physical Design, 2014

Unlocking the true potential of 3D CPUs with micro-fluidic cooling.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013
Co-optimization of TSV assignment and micro-channel placement for 3D-ICs.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Online TSV health monitoring and built-in self-repair to overcome aging.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

High performance 3D stacked DRAM processor architectures with micro-fluidic cooling.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013


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