Changhyun Pyo

According to our database, Changhyun Pyo authored at least 3 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces.

Boram Kim, Hankyu Chi, Hyeongjun Ko, Sang-Yeon Byeon, Sungkwon Lee, Changhyun Pyo, Seulgi Kim, Byungjun Kang, Eunji Song, Kwangjin Na, Jin-Youp Cha, Hyesoo Kim, Shinyoung Park, Woo-Seok Choi, Kyunghoon Kim, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory.

Seoyoon Jang, Sangouk Jeon, Kwanghyun Shin, Dongkwon Lee, Hankyu Chi, Wookjin Shin, Changhyun Pyo, Jaeha Kim, Dongsuk Jeon

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2022

A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS.

Eunsang Lee, Changhyun Pyo, Sanghun Lee, Jaeduk Han

IEEE Trans. Circuits Syst. I Regul. Pap., 2022