Hyeongjun Ko
Orcid: 0000-0002-5025-6771
According to our database1,
Hyeongjun Ko
authored at least 10 papers
between 2015 and 2024.
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Bibliography
2024
A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2021
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer.
IEEE J. Solid State Circuits, 2021
2019
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2017
An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface.
Proceedings of the International SoC Design Conference, 2017
2015
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications.
Proceedings of the Symposium on VLSI Circuits, 2015
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015