Chao-Lin Lee

Orcid: 0000-0002-4619-3843

Affiliations:
  • National Tsing Hua University, Hsinchu City, Taiwan


According to our database1, Chao-Lin Lee authored at least 16 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Accelerating AI performance with the incorporation of TVM and MediaTek NeuroPilot.
Connect. Sci., December, 2023

Accelerating AI Applications with Sparse Matrix Compression in Halide.
J. Signal Process. Syst., May, 2023

SIMD Everywhere Optimization from ARM NEON to RISC-V Vector Extensions.
CoRR, 2023

Support of Sparse Tensor Computing for MLIR HLS.
Proceedings of the 52nd International Conference on Parallel Processing Workshops, 2023

2022
Efficient Realization of Decision Trees for Real-Time Inference.
ACM Trans. Embed. Comput. Syst., November, 2022

Register-Pressure Aware Predicator for Length Multiplier of RVV.
Proceedings of the Workshop Proceedings of the 51st International Conference on Parallel Processing, 2022

2021
Accelerate Binarized Neural Networks with Processing-in-Memory Enabled by RISC-V Custom Instructions.
Proceedings of the ICPP Workshops 2021: 50th International Conference on Parallel Processing, 2021

Support Convolution of CNN with Compression Sparse Matrix Multiplication Flow in TVM.
Proceedings of the ICPP Workshops 2021: 50th International Conference on Parallel Processing, 2021

2020
Experiment and enabled flow for GPGPU-Sim simulators with fixed-point instructions.
J. Syst. Archit., 2020

Experiments and optimizations for TVM on RISC-V Architectures with P Extension.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

Devise Sparse Compression Schedulers to Enhance FastText Methods.
Proceedings of the ICPP Workshops '20: Workshops, Edmonton, AB, Canada, August 17-20, 2020, 2020

2019
Sparse-Matrix Compression Primitives with OpenCL Framework to Support Halide.
Proceedings of the International Workshop on OpenCL, 2019

Accelerate DNN Performance with Sparse Matrix Compression in Halide.
Proceedings of the 48th International Conference on Parallel Processing, 2019

2018
Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files.
ACM Trans. Design Autom. Electr. Syst., 2018

Enable the Flow for GPGPU-Sim Simulators with Fixed-Point Instructions.
Proceedings of the 47th International Conference on Parallel Processing, 2018

2017
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017


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