Ching-Te Chiu
Orcid: 0000-0003-2818-1125
According to our database1,
Ching-Te Chiu
authored at least 113 papers
between 1992 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
EfficientNet-eLite: Extremely Lightweight and Efficient CNN Models for Edge Devices by Network Candidate Search.
J. Signal Process. Syst., May, 2023
PGT-Net: Progressive Guided Multi-task Neural Network for Small-area Wet Fingerprint Denoising and Recognition.
CoRR, 2023
Multiple Training Stage Image Enhancement Enrolled With CCRGAN Pseudo Templates for Large Area Dry Fingerprint Recognition.
IEEE Access, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the Asia Pacific Signal and Information Processing Association Annual Summit and Conference, 2023
CPGAN: Collective Punishment Generative Adversarial Network for Dry Fingerprint Image Enhancement.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
RGBD-based Hardware Friendly Head Pose Estimation System via Convolutional attention module.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Object Detection in RGB-D Images via Anchor Box with Multi-Reduced Region Proposal Network and Multi-Pooling.
J. Signal Process. Syst., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2021
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2021
2020
J. Signal Process. Syst., 2020
Real-Time Object Detection With Reduced Region Proposal Network via Multi-Feature Concatenation.
IEEE Trans. Neural Networks Learn. Syst., 2020
Multi-teacher knowledge distillation for compressed video action recognition based on deep learning.
J. Syst. Archit., 2020
ESSA: An energy-Aware bit-Serial streaming deep convolutional neural network accelerator.
J. Syst. Archit., 2020
Semantic Segmentation via Enhancing Context Information by Fusing Multiple High-Level Features.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Depth Estimation From Single Image Through Multi-Path-Multi-Rate Diverse Feature Extractor.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Object Detection with Color and Depth Images with Multi-Reduced Region Proposal Network and Multi-Pooling.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Fast Single-View 3D Object Reconstruction with Fine Details Through Dilated Downsample and Multi-Path Upsample Deep Neural Network.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Deep Neural Network Compression with Knowledge Distillation Using Cross-Layer Matrix, KL Divergence and Offline Ensemble.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2020
2019
Filter-based deep-compression with global average pooling for convolutional networks.
J. Syst. Archit., 2019
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019
Multi-teacher Knowledge Distillation for Compressed Video Action Recognition on Deep Neural Networks.
Proceedings of the IEEE International Conference on Acoustics, 2019
Real-time Object Detection via Pruning and a Concatenated Multi-feature Assisted Region Proposal Network.
Proceedings of the IEEE International Conference on Acoustics, 2019
2018
J. Signal Process. Syst., 2018
Filter-based Deep-Compression with Global Average Pooling for Convolutional Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
PVDC: A Binary Descriptor Using Pore-Valley Disk Code Structure for High-Resolution Partial Fingerprint Recognition.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
2017
IET Image Process., 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 International Conference on Computing, 2017
Motion clustering with hybrid-sample-based foreground segmentation for moving cameras.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
A cost-effective minutiae disk code for fingerprint recognition and its implementation.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
2015
Edge Curve Scaling and Smoothing with Cubic Spline Interpolation for Image Up-Scaling.
J. Signal Process. Syst., 2015
Editorial: Signal Processing for Communication/Biomedical Systems and Reliability Improvement.
J. Signal Process. Syst., 2015
IEEE Trans. Multim., 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015
2014
A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2014
Boosted multi-class object detection with parallel hardware implementation for real-time applications.
Proceedings of the IEEE International Conference on Acoustics, 2014
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
2013
Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Edge curve scaling and smoothing with cubic spline interpolation for image upscaling.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the IEEE International Conference on Image Processing, 2013
Depth-based posture recognition by radar and vision fusion for real-time applications.
Proceedings of the IEEE International Conference on Acoustics, 2013
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013
Low cost illumination invariant face recognition by down-up sampling self quotient image.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013
2012
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking.
J. Signal Process. Syst., 2012
A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 International Conference on Connected Vehicles and Expo, 2012
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
2011
Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform.
J. Signal Process. Syst., 2011
A 0.64 mm <sup>2</sup> Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction.
IEEE Trans. Very Large Scale Integr. Syst., 2011
BiTA/SWCE: Image Enhancement With Bilateral Tone Adjustment and Saliency Weighted Contrast Enhancement.
IEEE Trans. Circuits Syst. Video Technol., 2011
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Low visual difference virtual high dynamic range image synthesizer from a single legacy image.
Proceedings of the 18th IEEE International Conference on Image Processing, 2011
Proceedings of the 18th IEEE International Conference on Image Processing, 2011
Curve-based and image-based JND contrast analysis for inverse tone mapping operators.
Proceedings of the 18th IEEE International Conference on Image Processing, 2011
Handover Delay Reduction and Buffer-Based Data Recovery Scheme for Inter Multicast Broadcast Service Zone.
Proceedings of the Global Communications Conference, 2011
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Switching Bilateral Filter With a Texture/Noise Detector for Universal Noise Removal.
IEEE Trans. Image Process., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Proceedings of the International Conference on Image Processing, 2009
Proceedings of the International Conference on Image Processing, 2009
2008
A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video.
Proceedings of the International Conference on Image Processing, 2008
A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007
Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video.
Proceedings of the International Conference on Image Processing, 2007
Block-Based Gradient Domain High Dynamic Range Compression Design for Real-Time Applications.
Proceedings of the International Conference on Image Processing, 2007
A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Proceedings of the Fifth IEEE International Symposium on Network Computing and Applications, 2006
2005
A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005
1994
Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transforms.
IEEE Trans. Circuits Syst. Video Technol., 1994
1993
Unified parallel lattice structures for time-recursive discrete cosine/sine/Hartley transforms.
IEEE Trans. Signal Process., 1993
Proceedings of the IEEE International Conference on Acoustics, 1993
1992
VLSI Algorithms and Architectures for Time-Recursive Discrete Sinuoidal Transforms with Applications to Real-Time Video Communications.
PhD thesis, 1992
Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems.
IEEE Trans. Circuits Syst. Video Technol., 1992