Hsiang-Yun Cheng

Orcid: 0000-0002-8983-9835

Affiliations:
  • Academia Sinica, Taiwan


According to our database1, Hsiang-Yun Cheng authored at least 27 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Tensor Movement Orchestration in Multi-GPU Training Systems.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications.
Proceedings of the International Conference on Compilers, 2023

2022
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators.
ACM Trans. Embed. Comput. Syst., 2022

Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging.
Proceedings of the 11th IEEE Non-Volatile Memory Systems and Applications Symposium, 2022

Retinex Based on Weaken Factor with Truncated AGCWD for Backlight Image Enhancement.
Proceedings of the IEEE International Conference on Consumer Electronics, 2022

Efficient Bad Block Management with Cluster Similarity.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Future Computing Platform Design: A Cross-Layer Design Approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration.
IEEE Trans. Computers, 2019

Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling.
CoRR, 2018

DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling.
IEEE Comput. Archit. Lett., 2017

Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

2016
Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015
Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference.
ACM Trans. Design Autom. Electr. Syst., 2015

EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors.
ACM Trans. Archit. Code Optim., 2015

Core vs. uncore: the heart of darkness.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2010
Memory Latency Reduction via Thread Throttling.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010


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