Chaolong Xu

According to our database, Chaolong Xu authored at least 11 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers.

Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang

IEEE Trans. Very Large Scale Integr. Syst., April, 2025

An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver.

Mingche Lai, Chaolong Xu, Fangxu Lv, Jiaqing Xu, Qiang Wang, Yang Ou, Xiaoyue Hu, Cewen Liu, Zhouhao Yang

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2025

A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver.

Cewen Liu, Xingyun Qi, Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai

Microelectron. J., 2025

A lightweight underwater object detection with enhanced detail and edge-aware feature fusion.

Chaolong Xu, Zhibin Xie

Digit. Signal Process., 2025

2024

Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.

Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE.

Xiaoyue Hu, Fangxu Lv, Mingche Lai, Zhang Luo, Qiang Wang, Chaolong Xu, Ruotian Yin, Zhouhao Yang, Cewen Liu

IEICE Electron. Express, 2024

FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver.

Chaolong Xu, Fangxu Lv, Zhengbin Pang, Liquan Xiao, Zhouhao Yang

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver.

Chaolong Xu, Fangxu Lv, Mingche Lai, Zhang Luo, Xingyun Qi, Jiaqing Xu, Qiang Wang, Liquan Xiao, Cewen Liu, Hua Xu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023

A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks.

Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu

Proceedings of the IEEE International Conference on High Performance Computing & Communications, 2023

2022

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.

Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi

Microelectron. J., 2022

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication.

Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu

IEEE Access, 2022