Geng Zhang

According to our database, Geng Zhang authored at least 12 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 61.4 Gb/s/mm Wireline Transceiver Using a 7 bit-Over-8 Lane Symmetric Correlated Coding for High-Density Interconnects.

Mingche Lai, Geng Zhang, Fangxu Lv, Liquan Xiao, Xuqiang Zheng, Heng Huang, Kewei Xin, Liangyong Yuan, Ruixiao Kuai, Bolin Ren, Ruotian Yin, Guohe Zhang, Chao Fan

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026

A 157-Gb/s/mm 1.55-pJ/bit Correlated PAM4 Transceiver with Immunity to Crosstalk, Simultaneous Switching and Common-Mode Noise for High-Density Interconnect in 28nm CMOS.

Geng Zhang, Fangxu Lv, Mingche Lai, Liquan Xiao, Ruixiao Kuai, Liangyong Yuan, Chao Fan, Lizhou Wu, Guohe Zhang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers.

Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang

IEEE Trans. Very Large Scale Integr. Syst., April, 2025

2024

Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.

Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface.

Bolin Ren, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu

Microelectron. J., 2024

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs.

Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang

Microelectron. J., 2024

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process.

Wenchen Wang, Fangxu Lv, Zhengbin Pang, Heng Huang, Zhang Luo, Xingyun Qi, Jiaqing Xu, Geng Zhang, Kewei Xin, Chengzhuo Zhao

IEICE Electron. Express, 2024

2023

Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications.

Qing Liu, Heming Wang, Fangxu Lv, Geng Zhang, Dongbin Lv

Proceedings of the 4th International Conference on Computer Engineering and Intelligent Control, 2023

A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks.

Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu

Proceedings of the IEEE International Conference on High Performance Computing & Communications, 2023

2022

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.

Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi

Microelectron. J., 2022

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication.

Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu

IEEE Access, 2022

2021

A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface.

Geng Zhang, Fangxu Lv, Zhengbin Pang, Heming Wang, Dongbin Lv, Tao Liu, Jinwang Zhang

Proceedings of the 14th IEEE International Conference on ASIC, 2021