Charalampos Bezaitis

According to our database, Charalampos Bezaitis authored at least 4 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators.

Yaman Umuroglu, Christoph Berganski, Felix Jentzsch, Michal Danilowicz, Tomasz Kryjak, Charalampos Bezaitis, Magnus Själander, Ian Colbert, Thomas B. Preußer, Jakoba Petri-Koenig, Michaela Blott

CoRR, August, 2025

2022

Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification.

Angelos Kyriakos, Elissaios-Alexios Papatheofanous, Charalampos Bezaitis, Dionysios I. Reisis

J. Imaging, 2022

Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space.

Vasileios Leon, Elissaios-Alexios Papatheofanous, George Lentaris, Charalampos Bezaitis, Nikolaos Mastorakis, Georgios Bampilis, Dionysios I. Reisis, Dimitrios Soudris

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2021

FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks.

Vasileios Leon, Charalampos Bezaitis, George Lentaris, Dimitrios Soudris, Dionysios I. Reisis, Elissaios-Alexios Papatheofanous, Angelos Kyriakos, Aubrey Dunne, Arne Samuelsson, David Steenari

Proceedings of the 28th IEEE International Conference on Electronics, 2021