Charles R. Kime

IEEE Trans. Computers, 1997

1996

MFBIST: A BIST Method for Random Pattern Resistant Circuits.

[BibT_eX]

[DOI]

Mohammed F. AlShaibi

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995

Partial scan flip-flop selection by use of empirical testability.

[BibT_eX]

[DOI]

Kee Sup Kim

J. Electron. Test., 1995

1994

ICAT: incremental combinational ATPG.

[BibT_eX]

[DOI]

Byung S. So

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Multiple weighted cellular automata.

[BibT_eX]

[DOI]

Danial J. Neebel

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Fixed-Biased Pseudorandom Built-In Self-Test for Random-Pattern-Resistant Circuits.

[BibT_eX]

[DOI]

Mohammed F. AlShaibi

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993

A fault simulation method: Parallel pattern critical path tracing.

[BibT_eX]

[DOI]

Byung S. So

J. Electron. Test., 1993

A Tutorial on Built-In Self-Test, Part 2: Applications.

[BibT_eX]

[DOI]

Vishwani D. Agrawal

IEEE Des. Test Comput., 1993

A Tutorial on Built-in Self-Test. I. Principles.

[BibT_eX]

[DOI]

Vishwani D. Agrawal

IEEE Des. Test Comput., 1993

Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation.

[BibT_eX]

[DOI]

Danial J. Neebel

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Partial Scan Using Reverse Direction Empirical Testability.

[BibT_eX]

[DOI]

Kee Sup Kim

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992

Test Scheduling in High Performance VLSI System Implementations.

[BibT_eX]

[DOI]

John Y. Sayah

IEEE Trans. Computers, 1992

1990

Computer-aided design of pseudoexhaustive BIST for semiregular circuits.

[BibT_eX]

[DOI]

Chau-Chin Su

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Multiple path sensitization for hierarchical circuit testing.

[BibT_eX]

[DOI]

Chau-Chin Su

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Partial Scan by Use of Empirical Testability.

[BibT_eX]

[DOI]

Kee Sup Kim

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989

Scheduling unequal length tests in high performance VLSI system implementations.

[BibT_eX]

[DOI]

John Y. Sayah

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988

A concurrent testing technique for digital circuits.

[BibT_eX]

[DOI]

Rajiv Sharma

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Test Scheduling and Control for VLSI Built-In Self-Test.

[BibT_eX]

[DOI]

Gary L. Craig

IEEE Trans. Computers, 1988

Concurrent Off-Phase Built-in Self-Test of Dormant Logic.

[BibT_eX]

[DOI]

Leon J. Sigal

Proceedings of the Proceedings International Test Conference 1988, 1988

Impact of Testability Standards on University Research and Instruction.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1988, 1988

1985

Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults.

[BibT_eX]

Gary L. Craig

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

Diagnosis in the Presence of Known Faults.

[BibT_eX]

[DOI]

John A. McPherson

IEEE Trans. Computers, 1984

A Built-In Test Methodology for VLSI Data Paths.

[BibT_eX]

Proceedings of the Proceedings International Test Conference 1984, 1984

1982

WISPAC: A Parallel Array Computer for Simulation Applications.

[BibT_eX]

Proceedings of the Parallel and Large-Scale Computers: Performance, 1982

1979

A Two-Level Diagnostic Model for Digital Systems.

[BibT_eX]

[DOI]

John A. McPherson

IEEE Trans. Computers, 1979

An Abstract Model for Digital System Fault Diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1979

1976

A Module-Level Testing Approach for Combinational Networks.

[BibT_eX]

[DOI]

Ramachendra P. Batni

IEEE Trans. Computers, 1976

1975

System Fault Diagnosis: Closure and Diagnosability with Repair.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1975

System Fault Diagnosis: Masking, Exposure, and Diagnosability Without Repair.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1975

Comments on "Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences".

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1975

Fault Tolerant Computing: An Introduction and a Perspective.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1975

1974

An Efficient Algorithm for Finding an Irredundant Set Cover.

[BibT_eX]

[DOI]

Ramachendra P. Batni

J. ACM, 1974

1972

Improved Procedures for Determining Diagnostic Resolution.

[BibT_eX]

[DOI]

James C. Bassett

IEEE Trans. Computers, 1972

1971

Structural Factors in the Fault Diagnosis of Combinational Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1971

1970

An Analysis Model for Digital System Diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1970

1966

An organization for checking experiments on sequential circuits.

[BibT_eX]

[DOI]