Chenkun Wang

Orcid: 0000-0001-8271-4039

Affiliations:
  • University of California, Riverside, CA, USA


According to our database1, Chenkun Wang authored at least 10 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS.
IEEE Access, 2020

2019
A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
A study of impacts of ESD protection on 28/38GHz RF switches in 45nm SOI CMOS for 5G mobile applications.
Proceedings of the 2018 IEEE Radio and Wireless Symposium, 2018

3D heterogeneous integration enabling future RF ICs.
Proceedings of the 2018 IEEE Radio and Wireless Symposium, 2018

2017
More-Than-Moore: 3D heterogeneous integration into CMOS technologies.
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017

TLP measurement and analysis of graphene NEMS switches for on-chip ESD protection.
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017

Key note: Integrated design-for-reliability for ICs.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Characterization of single-crystalline graphene ESD interconnects.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015
TLP evaluation of ESD protection capability of graphene micro-ribbons for ICs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015


  Loading...