Fei Lu

Orcid: 0000-0002-4928-2171

Affiliations:
  • University of California at Riverside, USA


According to our database1, Fei Lu authored at least 15 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS.
IEEE Access, 2020

2019
A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
A study of impacts of ESD protection on 28/38GHz RF switches in 45nm SOI CMOS for 5G mobile applications.
Proceedings of the 2018 IEEE Radio and Wireless Symposium, 2018

2017
More-Than-Moore: 3D heterogeneous integration into CMOS technologies.
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017

TLP measurement and analysis of graphene NEMS switches for on-chip ESD protection.
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017

Key note: Integrated design-for-reliability for ICs.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Characterization of single-crystalline graphene ESD interconnects.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015
TLP evaluation of ESD protection capability of graphene micro-ribbons for ICs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Function-based ESD protection circuit design verification for BGA pad-ring array.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection.
IEEE J. Solid State Circuits, 2014

Scalable behavior modeling for SCR based ESD protection structures for circuit simulation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Heterogeneous integration of nano enabling devices for 3D ICs.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Scalable behavior modeling for 3D field-programmable ESD protection structures.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013


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