Albert Z. Wang

Orcid: 0000-0002-0581-5765

Affiliations:
  • University of California, Riverside, CA, USA
  • Illinois Institute of Technology, Chicago, IL, USA


According to our database1, Albert Z. Wang authored at least 79 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
On-chip ESD Protection Design Methodologies by CAD Simulation.
ACM Trans. Design Autom. Electr. Syst., January, 2024

2023
Visible Light Communication Based Smart IoT Technologies and Applications.
Proceedings of the IEEE International Conference on Smart Internet of Things, 2023

A 38GHz SPDT Traveling Wave Switch with 5A CDM ESD Protection in 45nm PDSOI for 5G System.
Proceedings of the IEEE Radio and Wireless Symposium, 2023

Design Implementation of A Hybrid VLP/PLC-Based Indoor Tracking System for Smart Hospitals.
Proceedings of the IEEE International Conference on Consumer Electronics, 2023

ESD Protection is About Circuit Design: Practices and Perspectives.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

Design for EMI Immunity and ESD Protection for Wearable and Flexible ICs (Invited).
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2021
Integrated Design of Low Complexity RSS Based Visible Light Indoor Positioning and Power-Line Communication System for Smart Hospitals.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021

2020
A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS.
IEEE Access, 2020

VLC-Enabled Human-Aware Building Management System.
Proceedings of the Distributed, Ambient and Pervasive Interactions, 2020

2019
A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Visible Light Communication Cyber-Physical Systems-on- Chip for Smart Cities.
J. Commun., 2019

Developing 3D Heterogeneous Structures for Future Chips.
Proceedings of the International Conference on IC Design and Technology, 2019

A Study of Optical Tag Detection Using Rolling Shutter Based Visible Light Communications.
Proceedings of the 2019 IEEE Global Communications Conference, 2019

2018
A study of impacts of ESD protection on 28/38GHz RF switches in 45nm SOI CMOS for 5G mobile applications.
Proceedings of the 2018 IEEE Radio and Wireless Symposium, 2018

3D heterogeneous integration enabling future RF ICs.
Proceedings of the 2018 IEEE Radio and Wireless Symposium, 2018

2017
A quantitative design methodology for high-speed interpolation/averaging ADCs.
Integr., 2017

More-Than-Moore: 3D heterogeneous integration into CMOS technologies.
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017

Optimization of suspended graphene NEMS devices for electrostatic discharge applications.
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017

TLP measurement and analysis of graphene NEMS switches for on-chip ESD protection.
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017

Key note: Integrated design-for-reliability for ICs.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Characterization of single-crystalline graphene ESD interconnects.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015
Vehicular optical ranging and communication system.
EURASIP J. Wirel. Commun. Netw., 2015

Hemispherical Lens Featured Beehive Structure Receiver on Vehicular Massive MIMO Visible Light Communication System.
Proceedings of the Internet of Vehicles - Safe and Intelligent Mobility, 2015

TLP evaluation of ESD protection capability of graphene micro-ribbons for ICs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Function-based ESD protection circuit design verification for BGA pad-ring array.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection.
IEEE J. Solid State Circuits, 2014

Introduction to the Special Section on the 2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.
IEEE J. Solid State Circuits, 2014

Scalable behavior modeling for SCR based ESD protection structures for circuit simulation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Post-Si Programmable ESD Protection Circuit Design: Mechanisms and Analysis.
IEEE J. Solid State Circuits, 2013

Integrated stacked-Spiral RF inductor with nanopowder magnetic Core.
J. Circuits Syst. Comput., 2013

An optimized UWB correlator design with the consideration of the impacts from the ESD protection devices.
Sci. China Inf. Sci., 2013

Heterogeneous integration of nano enabling devices for 3D ICs.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Design and analysis of full-chip HV ESD protection in BCD30V for mixed-signal ICs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A multi-mode complex bandpass filter with gm-assisted power optimization and I/Q calibration.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Scalable behavior modeling for 3D field-programmable ESD protection structures.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Concurrent design of ESD protection and ICs for optimization and prediction.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Quantitative analysis for high speed interpolated/averaging ADC.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design technique.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Folding and interpolation ADC design methodology.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A design technique overview on broadband RF ESD protection circuit designs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Field programmable SONOS ESD protection design.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs.
IEEE Trans. Ind. Electron., 2011

Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS.
IEEE J. Solid State Circuits, 2011

Design Matrix Analysis for Capacitive Interpolation Flash ADC.
J. Low Power Electron., 2011

Co-design of ESD protection and UWB RF front-end ICs.
Sci. China Inf. Sci., 2011

Low power 3.1-10.6 GHz IR-UWB transmitter for Gbps wireless communications.
Sci. China Inf. Sci., 2011

2010
A 52-mW 3.1-10.6-GHz Fully Integrated Correlator for IR-UWB Transceivers in 0.18 μm CMOS.
IEEE Trans. Ind. Electron., 2010

1.8 pJ/Pulse Programmable Gaussian Pulse Generator for Full-Band Noncarrier Impulse-UWB Transceivers in 90-nm CMOS.
IEEE Trans. Ind. Electron., 2010

2009
A Single-chip 33pJ/pulse 5th-derivative Gaussian based IR-UWB Transmitter in 0.13µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A Wideband three-stage rail-to-rail power amplifier driving large capacitive load.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Varying Pulse Width Second Order Derivative Gaussian Pulse Generator for UWB Transceivers in CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A Pulse-Based Full-Band UWB Transceiver SoC in 0.18μm SiGe BiCMOS.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

A 3V 110µW 3.1 ppm/°C curvature-compensated CMOS bandgap reference.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Introduction to the Special Issue on the IEEE 2004 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2005

A 12 bits/200 MHz resolution/sampling/power-optimized ADC in 0.25µm SiGe BiCMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 5 GHz sub-harmonic direct down-conversion mixer for dual-band system in 0.35µm SiGe BiCMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Will continued process-node shrinks kill high-performance analog design?
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Body wellness without wires.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Introduction to the Special Issue on the IEEE 2003 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2004

ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

L-simulator: a magPEEC-based new CAD tool for simulating magnetic-enhanced IC inductors of 3D arbitrary geometry.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 3D mixed-mode ESD protection circuit simulation-design methodology.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A mixed-mode ESD protection circuit simulation-design methodology.
IEEE J. Solid State Circuits, 2003

Mixed-mode ESD protection circuit simulation-design methodology.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Bonding-pad-oriented on-chip ESD protection structures for ICs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Recent developments in ESD protection for RF ICs.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
A technology-independent CAD tool for ESD protection device extraction: ESDExtractor.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

ESD protection design for RF integrated circuits: new challenges.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology.
IEEE J. Solid State Circuits, 2001

An ESD protection circuit for mixed-signal ICs.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
A new design for complete on-chip ESD protection.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
A low-triggering circuitry for dual-direction ESD protection.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999


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