Israel Koren

According to our database1, Israel Koren authored at least 211 papers between 1977 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of one.

Awards

IEEE Fellow

IEEE Fellow 1991, "For contributions to the field of fault-tolerant VLSI systems.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Designing a secure DRAM+NVM hybrid memory module.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Improving Communication and Load Balancing with Thread Mapping in Manycore Systems.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

Analysis of Single Event Upsets Based on Digital Cameras with Very Small Pixels.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
AdaFT: A Framework for Adaptive Fault Tolerance for Cyber-Physical Systems.
ACM Trans. Embedded Comput. Syst., 2017

Affinity-Based Thread and Data Mapping in Shared Memory Systems.
ACM Comput. Surv., 2017

Experimental and analytical study of Xeon Phi reliability.
Proceedings of the International Conference for High Performance Computing, 2017

Keynote speech: IGSC 2017: Green computing through adaptive multi-core architectures.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Exploring soft errors (SEUs) with digital imager pixels ranging from 7 to 1.3 μm.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

CAROL-FI: an Efficient Fault-Injection Tool for Vulnerability Evaluation of Modern HPC Parallel Accelerators.
Proceedings of the Computing Frontiers Conference, 2017

Data mining the memory access stream to detect anomalous application behavior.
Proceedings of the Computing Frontiers Conference, 2017

2016
Exploring Heterogeneity within a Core for Improved Power Efficiency.
IEEE Trans. Parallel Distrib. Syst., 2016

A dynamic block-level execution profiler.
Parallel Computing, 2016

Online Inertia-Based Temperature Estimation for Reliability Enhancement.
J. Low Power Electronics, 2016

Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Improving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classification.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Experimental study and analysis of soft and permanent errors in digital cameras.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Energy efficient deeply fused dot-product multiplication architecture.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Does the Sharing of Execution Units Improve Performance/Power of Multicores?
ACM Trans. Embedded Comput. Syst., 2015

Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Improving processor lifespan and energy consumption using DVFS based on ILP monitoring.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Single Event Upsets and Hot Pixels in digital imagers.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating.
IEEE Trans. VLSI Syst., 2014

A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks.
IEEE Trans. Emerging Topics Comput., 2014

Scheduling imprecise task graphs for real-time applications.
IJES, 2014

A low energy dual-mode adder.
Computers & Electrical Engineering, 2014

Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Improved correction for hot pixels in digital imagers.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
A Study on the Use of Performance Counters to Estimate Power in Microprocessors.
IEEE Trans. on Circuits and Systems, 2013

Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management.
J. Low Power Electronics, 2013

Countermeasures against EM analysis for a secured FPGA-based AES implementation.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

A study on polymorphing superscalar processor dynamically to improve power efficiency.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Adaptive fault-tolerance fault-tolerance for cyber-physical systems.
Proceedings of the International Conference on Computing, Networking and Communications, 2013

On dynamic polymorphing of a superscalar core for improving energy efficiency.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

An evaluation of an AES implementation protected against EM analysis.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Improved image accuracy in Hot Pixel degraded digital cameras.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Interaction Between Fault Attack Countermeasures and the Resistance Against Power Analysis Attacks.
Proceedings of the Fault Analysis in Cryptography, 2012

The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating.
IEEE Trans. VLSI Syst., 2012

Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing.
ACM Trans. Design Autom. Electr. Syst., 2012

Fault Injection Attacks on Cryptographic Devices: Theory, Practice, and Countermeasures.
Proceedings of the IEEE, 2012

On Reliability Trojan Injection and Detection.
J. Low Power Electronics, 2012

Scalable Thread Scheduling in Asymmetric Multicores for Power Efficiency.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

Dynamic Thread Scheduling in Asymmetric Multicores to Maximize Performance-per-Watt.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Do more camera pixels result in a better picture?
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

A Study of the Impact of Computational Delays in Missile Interception Systems.
Proceedings of the ICINCO 2012 - Proceedings of the 9th International Conference on Informatics in Control, Automation and Robotics, Volume 1, Rome, Italy, 28, 2012

Cost Functions for Scheduling Tasks in Cyber-physical Systems.
Proceedings of the ICINCO 2012 - Proceedings of the 9th International Conference on Informatics in Control, Automation and Robotics, Volume 1, Rome, Italy, 28, 2012

Runtime architecture adaptation for energy management in embedded real-time systems.
Proceedings of the 2012 International Green Computing Conference, 2012

A mechanism to verify cache coherence transactions in multicore systems.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Relating digital imager defect rates to pixel size, sensor area and ISO.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Utilization-Based Resource Partitioning for Power-Performance Efficiency in SMT Processors.
IEEE Trans. Parallel Distrib. Syst., 2011

Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation.
Proceedings of the RFID. Security and Privacy - 7th International Workshop, 2011

Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Nanoscale Application Specific Integrated Circuits.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

An Architecture to Enable Life Cycle Testing in CMPs.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Biased Voting for Improved Yield in Nanoscale Fabrics.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Predicting Pixel Defect Rates Based on Image Sensor Parameters.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Towards logic functions as the device.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

A study on performance benefits of core morphing in an asymmetric multicore processor.
Proceedings of the 28th International Conference on Computer Design, 2010

Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Tradeoffs in Imager Design with Respect to Pixel Defect Rates.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Countermeasures against fault attacks on software implemented AES: effectiveness and cost.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

2009
Event-driven adaptive duty-cycling in sensor networks.
IJSNet, 2009

Statistical identification and analysis of defect development in digital imagers.
Proceedings of the Digital Photography V, 2009

Characterization of Gain Enhanced In-Field Defects in Digital Imagers.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Automatic Detection of In-field eld Defect Growth in Image Sensors.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

An adaptive resource partitioning algorithm for SMT processors.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
Software-Based Failure Detection and Recovery in Programmable Network Interfaces.
IEEE Trans. Parallel Distrib. Syst., 2007

An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers.
IEEE Trans. Computers, 2007

TILTS: A Fast Architectural-Level Transient Thermal Simulation Method.
J. Low Power Electronics, 2007

Simulated Annealing Based Temperature Aware Floorplanning.
J. Low Power Electronics, 2007

An Adaptive Algorithm for Fault Tolerant Re-Routing in Wireless Sensor Networks.
Proceedings of the Fifth Annual IEEE International Conference on Pervasive Computing and Communications, 2007

Countermeasures against Branch Target Buffer Attacks.
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007

Identification of in-field defect development in digital image sensors.
Proceedings of the Digital Photography III, San Jose, CA, USA, January 29-30, 2007, 2007

Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Quantitative Analysis of In-Field Defects in Image Sensor Arrays.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Guest Editors' Introduction: Special Section on Fault Diagnosis and Tolerance in Cryptography.
IEEE Trans. Computers, 2006

Compiler-based adaptive fetch throttling for energy-efficiency.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

A Note on Error Detection in an RSA Architecture by Means of Residue Codes.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Testing and Validation of the CASA DCAS System.
Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2006

Software-Based Adaptive and Concurrent Self-Testing in Programmable Network Interfaces.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

Incorporating Error Detection in an RSA Architecture.
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

A Fault Attack Against the FOX Cipher Family.
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

On-Line Mapping of In-Field Defects in Image Sensor Arrays.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Technology Mapping for Reliability Enhancement in Logic Synthesis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Yield-aware Floorplanning.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

An ILP Formulation for Yield-driven Architectural Synthesis.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On-Line Identification of Faults in Fault-Tolerant Imagers.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Energy aware kernel for hard real-time systems.
Proceedings of the 2005 International Conference on Compilers, 2005

Effective analytical delay model for transistor sizing.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Synthesis of Saturating Counters Using Traditional and Non-Traditional Basic Counters.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
A Self-Correcting Active Pixel Sensor Using Hardware and Software Correction.
IEEE Design & Test of Computers, 2004

Application-Level Fault Tolerance in the Orbital Thermal Imaging Spectrometer.
Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

Energy-Aware Data Prefetching for General-Purpose Programs.
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Energy Characterization of Hardware-Based Data Prefetching.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Workshop on Fault Diagnosis and Tolerance in Cryptography.
Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004

An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Combining compiler and runtime IPC predictions to reduce energy in next generation architectures.
Proceedings of the First Conference on Computing Frontiers, 2004

Detecting Faults in Four Symmetric Key Block Ciphers.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003
Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters.
IEEE Trans. VLSI Syst., 2003

Cool-Cache: A compiler-enabled energy efficient data caching framework for embedded/multimedia processors.
ACM Trans. Embedded Comput. Syst., 2003

Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard.
IEEE Trans. Computers, 2003

System-level power-aware design techniques in real-time systems.
Proceedings of the IEEE, 2003

Optimizing the Yield of VLSI Circuits.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

A Voltage Scheduling Heuristic for Real-Time Task Graphs.
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003

Pre-Processing Input Data to Augment Fault Tolerance in Space Applications.
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003

Low Overhead Fault Tolerant Networking in Myrinet.
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003

Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

Saturating Counters: Application and Design Alternatives.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002
Filtering Random Graphs to Synthesize Interconnection Networks with Multiple Objectives.
IEEE Trans. Parallel Distrib. Syst., 2002

Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling.
Computer Architecture Letters, 2002

Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Towards energy-aware software-based fault tolerance in real-time systems.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

JMPI: Implementing the Message Passing Standard in Java.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Using Rational Approximations for Evaluating the Reliablity of Highly Reliable Systems.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

The Minimax Cache: An Energy-Efficient Framework for Media Processors.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations.
IEEE Trans. Computers, 2001

Importance Sampling to Evaluate Real-time System Reliability: A Case Study.
Simulation, 2001

Cool-cache for hot multimedia.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Reliability Enhancement of Analog-to-Digital Converters (ADCs).
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Advanced Fault-Tolerance Techniques for a Color Digital Camera-on-a-Chip.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Application-Level Fault Tolerance as a Complement to System-Level Fault Tolerance.
The Journal of Supercomputing, 2000

Guest Editors' Introduction - Special Issue on Computer Arithmetic.
IEEE Trans. Computers, 2000

Incorporating Yield Enhancement into the Floorplanning Process.
IEEE Trans. Computers, 2000

Should Yield be a Design Objective?
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Power-Aware Replication of Data Structures in Distributed Embedded Real-Time Systems.
Proceedings of the Parallel and Distributed Processing, 2000

The Effect of Placement on Yield for Standard Cell Designs.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

A Self-Correcting Active Pixel Camera.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
STATS: A framework for microprocessor and system-level design space exploration.
Journal of Systems Architecture, 1999

Determination of Yield Bounds Prior to Routing.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998
Measuring the Vulnerability of Interconnection Networks in Embedded Systems.
IPPS/SPDP Workshops, 1998

Surge Handling as a Measure of Real-Time System Dependability.
IPPS/SPDP Workshops, 1998

Yield and Routing Objectives in Floorplanning.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
On the effect of floorplanning on the yield of large area integrated circuits.
IEEE Trans. VLSI Syst., 1997

Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Crosstalk Minimization in Three-Layer HVH Channel Routing.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems.
Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1996
A Mean Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques.
International Journal of Parallel Programming, 1996

Trade-offs between yield and reliability enhancement [VLSI].
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
Complete and partial fault tolerance of feedforward neural nets.
IEEE Trans. Neural Networks, 1995

Architecture and technology tradeoffs in the design of next-generation multiprocessor servers.
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

Phantom redundancy: a high-level synthesis approach for manufacturability.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

The effect of spot defects on the parametric yield of long interconnection lines.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Layer assignment for yield enhancement.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Techniques for Yield Enhancement of VLSI Adders.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

An analytical model of high performance superscalar-based multiprocessors.
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1994
A statistical study of defect maps of large area VLSI IC's.
IEEE Trans. VLSI Syst., 1994

Connectivity and performance tradeoffs in the cascade correlation learning architecture.
IEEE Trans. Neural Networks, 1994

Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains.
IEEE Trans. Computers, 1994

The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis.
IEEE Trans. Computers, 1994

Tradeoffs in the Design of Single Chip Multiprocessors.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994

An Algorithm for Area and Delay Optimization of Sequential Machines through Decomposition.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

The Effect of Wire Length Minimization on Yield.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

A Yield Study of VLSI Adders.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits.
IEEE Trans. Computers, 1993

Construction of Minimal n-2-n Encoders for Any n.
Neural Computation, 1993

On Paths with the Shortest Average Arc Length in Weighted Graphs.
Discrete Applied Mathematics, 1993

Hybrid Number Representations with Bounded Carry Propagation Chains.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

An Interactive Yield Estimator as a VLSI CAD Tool.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Does the Floorplan of a Chip Affect Its Yield?
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Topological Optimization of PLAs for Yield Enhancement.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Mapping algorithms onto a multiple-chip data-driven array.
Proceedings of the International Conference on Application-Specific Array Processors, 1993

The design of a 64-bit integer multiplier/divider unit.
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

Computer arithmetic algorithms.
Prentice Hall, ISBN: 978-0-13-151952-7, 1993

1992
Estimating the Potential Parallelism and Pipelining of Algorithms for Data Flow Machines.
J. Parallel Distrib. Comput., 1992

Balanced Block Spacing for VLSI Layout.
Discrete Applied Mathematics, 1992

1991
Discrete and Continuous Models for the Performance of Reconfigurable Multistage Systems.
IEEE Trans. Computers, 1991

A Random Distributed Algorithm to Embed Trees in Partially Faulty Processor Arrays.
J. Parallel Distrib. Comput., 1991

Using Simulated Annealing for Mapping Algorithms onto Data Driven Arrays.
Proceedings of the International Conference on Parallel Processing, 1991

1990
Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations.
IEEE Trans. Computers, 1990

Fault Tolerance in VLSI Circuits.
IEEE Computer, 1990

1988
Analysis of strategies for constructive general block placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Minimum-Diameter Cyclic Arrangements in Mapping Data-Flow Graphs onto VLSI Arrays.
Mathematical Systems Theory, 1988

A Data-Driven VLSI Array for Arbitrary Algorithms.
IEEE Computer, 1988

On the Bandwidth of a Multi-Stage Network in the Presence of Faulty Components.
Proceedings of the 8th International Conference on Distributed Computing Systems, 1988

Optimal Aspect Ratios of Building Blocks in VLSI.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems.
IEEE Trans. Computers, 1987

The Effect of Operation Scheduling on the Performance of a Data Flow Computer.
IEEE Trans. Computers, 1987

On Switching Policies for Modular Redundancy Fault-Tolerant Computing Systems.
IEEE Trans. Computers, 1987

The Concept and Implementation of Data-Driven Processor Arrays.
IEEE Computer, 1987

1986
Analysis of a Class of Recovery Procedures.
IEEE Trans. Computers, 1986

Comments on "The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors".
IEEE Trans. Computers, 1986

1985
Evaluating the Cost-Effectiveness of Switches in Processor Array Architectures.
Proceedings of the International Conference on Parallel Processing, 1985

1984
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays.
IEEE Trans. Computers, 1984

Embedding Tree Stuctures in VLlSI Hexagonal Arrays.
IEEE Trans. Computers, 1984

1983
A Direct Mapping of Algorithms onto VLSI Processing Arrays Based on the Data Flow Approach.
Proceedings of the International Conference on Parallel Processing, 1983

1981
On Classes of Positive, Negative, and Imaginary Radix Number Systems.
IEEE Trans. Computers, 1981

A Reconfigurable and Fault-Tolerant VLSI Multiprocessor Array.
Proceedings of the 8th Annual Symposium on Computer Architecture, 1981

1980
A New Approach to the Evaluation of the Reliability of Digital Systems.
IEEE Trans. Computers, 1980

1979
Reliability Analysis of N-Modular Redundancy Systems with Intermittent and Permanent Faults.
IEEE Trans. Computers, 1979

On the Properties of Sensitized Paths.
IEEE Trans. Computers, 1979

Analysis of the Signal Reliability Measure and an Evaluation Procedure.
IEEE Trans. Computers, 1979

1978
A Continous-Parameter Markov Model and Detection Procedures for Intermittent Faults.
IEEE Trans. Computers, 1978

A unified approach to a class of number systems.
Proceedings of the 4th IEEE Symposium on Computer Arithmetic, 1978

1977
Diagnosis of Intermittent Faults in Combinational Networks.
IEEE Trans. Computers, 1977

Sequential Fault Diagnosis in Combinational Networks.
IEEE Trans. Computers, 1977


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