Chia-Chien Weng

According to our database, Chia-Chien Weng authored at least 6 papers between 2007 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping.

Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, Shan-Chien Fang

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property.

Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng, Shan-Chien Fang, Chia-Chien Weng

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011

Black-box leakage power modeling for cell library and SRAM compiler.

Chun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan-Chien Fang, Ji-Jan Chen

Proceedings of the Design, Automation and Test in Europe, 2011

PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs.

Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh

Proceedings of the 48th Design Automation Conference, 2011

2010

Power aware SID-based simulator for embedded multicore DSP subsystems.

Cheng-Yen Lin, Po-Yu Chen, Chun-Kai Tseng, Chung-Wen Huang, Chia-Chieh Weng, Chi-Bang Kuan, Shih-Han Lin, Shi-Yu Huang, Jenq Kuen Lee

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2007

RT-level vector selection for realistic peak power simulation.

Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007