Ji-Jan Chen

According to our database1, Ji-Jan Chen authored at least 16 papers between 2005 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Diagnosis and Layout Aware (DLA) Scan Chain Stitching.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2013
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.
Proceedings of the 2013 IEEE International Test Conference, 2013

2012
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Black-box leakage power modeling for cell library and SRAM compiler.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Diagnosis of MRAM Write Disturbance Fault.
IEEE Trans. Very Large Scale Integr. Syst., 2010

An embedded wide-range and high-resolution CLOCK jitter measurement circuit.
Proceedings of the Design, Automation and Test in Europe, 2010

A Test Integration Methodology for 3D Integrated Circuits.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2008
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Experimental Results of Built-In Jitter Measurement for Gigahertz Clock.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Diagnosis for MRAM write disturbance fault.
Proceedings of the 2007 IEEE International Test Conference, 2007

A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement.
Proceedings of the 16th Asian Test Symposium, 2007

2006
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
On A Software-Based Self-Test Methodology and Its Application.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005


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