Wen-Tsan Hsieh

According to our database, Wen-Tsan Hsieh authored at least 8 papers between 2005 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2011

System power analysis with DVFS on ESL virtual platform.

Wen-Tsan Hsieh, Jen-Chieh Yeh, Shih-Che Lin, Hsing-Chuang Liu, Yi-Siou Chen

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs.

Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh

Proceedings of the 48th Design Automation Conference, 2011

System-level design exploration for 3-D stacked memory architectures.

Chi-Hung Lin, Wen-Tsan Hsieh, Hsien-Ching Hsieh, Chun-Nan Liu, Jen-Chieh Yeh

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010

PAC duo system power estimation at ESL.

Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2007

A Tableless Approach for High-Level Power Modeling Using Neural Networks.

Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou

J. Inf. Sci. Eng., 2007

An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model.

Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

A Scalable Power Modeling Approach for Embedded Memory Using LIB Format.

Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005

A novel approach for high-level power modeling of sequential circuits using recurrent neural networks.

Wen-Tsan Hsieh, Chih-Chieh Shiue, Chien-Nan Jimmy Liu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005