Chao-Wen Tzeng

According to our database1, Chao-Wen Tzeng authored at least 19 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Case study of process and design performance debugging with Digital Speed Sensor.
Proceedings of the VLSI Design, Automation and Test, 2015

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration.
IEEE Trans. Very Large Scale Integr. Syst., 2014

AC-Plus Scan Methodology for Small Delay Testing and Characterization.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Cell-Based Process Resilient Multiphase Clock Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Case study of yield learning through in-house flow of volume diagnosis.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A fully cell-based design for timing measurement of memory.
Proceedings of the 2011 IEEE International Test Conference, 2011

Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

QC-Fill: An X-Fill method for quick-and-cool scan test.
Proceedings of the Design, Automation and Test in Europe, 2009

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.
ACM Trans. Design Autom. Electr. Syst., 2008

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting.
IEEE Des. Test Comput., 2008

Two-Gear Low-Power Scan Test.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Robust paradigm for diagnosing hold-time faults in scan chains.
IET Comput. Digit. Tech., 2007