Chiraag Juvekar

According to our database, Chiraag Juvekar authored at least 21 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic Encryption.

Rashmi Agrawal, Leo de Castro, Chiraag Juvekar, Anantha P. Chandrakasan, Vinod Vaikuntanathan, Ajay Joshi

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption.

Rashmi Agrawal, Leo de Castro, Guowei Yang, Chiraag Juvekar, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Vinod Vaikuntanathan, Ajay Joshi

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022

Security Assessment of Phase-Based Ranging Systems in a Multipath Environment.

Arslan Riaz, Dylan Nash, Jonathan Ngo, Chiraag Juvekar, Phillip M. Nadeau, Tao Yu, Rabia Tugce Yazicigil

ACM J. Emerg. Technol. Comput. Syst., 2022

2021

CMOS THz-ID: A 1.6-mm² Package-Less Identification Tag Using Asymmetric Cryptography and 260-GHz Far-Field Backscatter Communication.

Muhammad Ibrahim Wasiq Khan, Mohamed I. Ibrahim, Chiraag Shashikant Juvekar, Wanyeong Jung, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Ruonan Han

IEEE J. Solid State Circuits, 2021

Does Fully Homomorphic Encryption Need Compute Acceleration?

Leo de Castro, Rashmi Agrawal, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Vinod Vaikuntanathan, Chiraag Juvekar, Ajay Joshi

IACR Cryptol. ePrint Arch., 2021

2020

Fast Vector Oblivious Linear Evaluation from Ring Learning with Errors.

Leo de Castro, Chiraag Juvekar, Vinod Vaikuntanathan

IACR Cryptol. ePrint Arch., 2020

29.8 THzID: A 1.6mm2 Package-Less Cryptographic Identification Tag with Backscattering and Beam-Steering at 260GHz.

Mohamed I. Ibrahim, Muhammad Ibrahim Wasiq Khan, Wanyeong Jung, Rabia Tugce Yazicigil, Chiraag Shashikant Juvekar, Anantha P. Chandrakasan, Ruonan Han

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications.

Utsav Banerjee, Andrew Wright, Chiraag Juvekar, Madeleine Waller, Arvind, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2019

Reconstructing Network Inputs with Additive Perturbation Signatures.

Nick Moran, Chiraag Juvekar

CoRR, 2019

2018

Hardware and protocols for authentication and secure computation.

Chiraag Shashikant Juvekar

PhD thesis, 2018

An Actively Detuned Wireless Power Receiver With Public Key Cryptographic Authentication and Dynamic Power Allocation.

Nachiket V. Desai, Chiraag Juvekar, Shubham Chandak, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2018

GAZELLE: A Low Latency Framework for Secure Neural Network Inference.

Chiraag Juvekar, Vinod Vaikuntanathan, Anantha P. Chandrakasan

IACR Cryptol. ePrint Arch., 2018

An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications.

Utsav Banerjee, Chiraag Juvekar, Andrew Wright, Arvind, Anantha P. Chandrakasan

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

A Nonvolatile Flip-Flop-Enabled Cryptographic Wireless Authentication Tag With Per-Query Key Update and Power-Glitch Attack Countermeasures.

Hyung-Min Lee, Chiraag Juvekar, Joyce Kwong, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2017

21.8 An actively detuned wireless power receiver with public key cryptographic authentication and dynamic power allocation.

Nachiket V. Desai, Chiraag Juvekar, Shubham Chandak, Anantha P. Chandrakasan

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

eeDTLS: Energy-Efficient Datagram Transport Layer Security for the Internet of Things.

Utsav Banerjee, Chiraag Juvekar, Samuel H. Fuller, Anantha P. Chandrakasan

Proceedings of the 2017 IEEE Global Communications Conference, 2017

2016

16.2 A Keccak-based wireless authentication tag with per-query key update and power-glitch attack countermeasures.

Chiraag Juvekar, Hyung-Min Lee, Joyce Kwong, Anantha P. Chandrakasan

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014

Decoder Hardware Architecture for HEVC.

Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan

Proceedings of the High Efficiency Video Coding (HEVC), Algorithms and Architectures, 2014

A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications.

Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2014

2013

HEVC interpolation filter architecture for quad full HD decoding.

Chao-Tsung Huang, Chiraag Juvekar, Mehul Tikekar, Anantha P. Chandrakasan

Proceedings of the 2013 Visual Communications and Image Processing, 2013

A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications.

Chao-Tsung Huang, Mehul Tikekar, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013