Chun-Hua Cheng

According to our database¹, Chun-Hua Cheng authored at least 29 papers between 2005 and 2020.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

Legend:

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In proceedings

Article

PhD thesis

Dataset

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Links

On csauthors.net:

Bibliography

2020

Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

2016

Power-mode-aware buffer synthesis for low-power clock skew minimization.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

IEICE Electron. Express, 2016

2014

Live demonstration: A low-power high-level synthesis system.

[BibT_eX]

[DOI]

Hua-Hsin Yeh

Chun-Hua Cheng

Shih-Hsu Huang

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Co-synthesis of data paths and clock control paths for minimum-period clock gating.

[BibT_eX]

[DOI]

Wen-Pin Tu

Shih-Hsu Huang

Chun-Hua Cheng

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A formal approach to slack-driven high-level synthesis.

[BibT_eX]

[DOI]

Hua-Hsin Yeh

Shih-Hsu Huang

Chun-Hua Cheng

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits.

[BibT_eX]

[DOI]

Wen-Pin Tu

Shih-Hsu Huang

Chun-Hua Cheng

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Simultaneous wafer bonding type selection and layer assignment for TSV count minimization.

[BibT_eX]

[DOI]

Chun-Hua Cheng

Wei-Shuo Tzeng

Shih-Hsu Huang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Accurate TSV Number Minimization in High-Level Synthesis.

[BibT_eX]

[DOI]

Chih-Hung Lee

Shih-Hsu Huang

Chun-Hua Cheng

J. Inf. Sci. Eng., 2011

Teaching three-dimensional system-in-package design automation in a semester course.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

2010

Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

J. Inf. Sci. Eng., 2010

2009

Minimum-Period Register Binding.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

Da-Chen Tzeng

J. Inf. Sci. Eng., 2009

Synthesis of Anti-Aging Gated Clock Designs.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

Song-Bin Pan

J. Inf. Sci. Eng., 2009

An ILP approach to surge current minimization in high-level synthesis.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Jheng-Fu Yeh

Chun-Hua Cheng

IEICE Electron. Express, 2009

Surge Current Minimization in High-level Synthesis.

[BibT_eX]

[DOI]

Jheng-Fu Yeh

Chun-Hua Cheng

Shih-Hsu Huang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Timing driven power gating in high-level synthesis.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Power-Management Scheduling for Peak Power Minimization.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

J. Inf. Sci. Eng., 2008

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Module binding for low power clock gating.

[BibT_eX]

[DOI]

Chun-Hua Cheng

Shih-Hsu Huang

Wen-Pin Tu

IEICE Electron. Express, 2008

2007

Operation scheduling for the synthesis of false loop free circuits.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

IEICE Electron. Express, 2007

Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential.

[BibT_eX]

[DOI]

Wei-Ting Yen

Shih-Hsu Huang

Chun-Hua Cheng

Proceedings of the Emerging Directions in Embedded and Ubiquitous Computing, 2007

Clock Period Minimization with Minimum Delay Insertion.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

An ILP Approach to the Slack Driven Scheduling Problem.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management.

[BibT_eX]

[DOI]

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Peak Power Minimization through Power Management Scheduling.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Operation Scheduling for False Loop Free Circuits.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Three-dimension scheduling under multi-cycle interconnect communications.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chung-Hsin Chiang

Chun-Hua Cheng

IEICE Electron. Express, 2005

A formal approach to the slack driven scheduling problem in high-level synthesis.

[BibT_eX]

[DOI]

Shih-Hsu Huang

Chun-Hua Cheng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Chun-Hua Cheng

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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