Chun-Nan Liu

According to our database1, Chun-Nan Liu authored at least 18 papers between 2003 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Multi-core system performance prediction and analysis at the ESL.
Int. J. Comput. Sci. Eng., 2014

A case study: 3-D stacked memory system architecture exploration by ESL virtual platform.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Baseband design and software-defined-radio implementation for LTE femtocell.
Proceedings of the 9th Asian Control Conference, 2013

Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part II: Application Programming.
J. Signal Process. Syst., 2011

Parallel Integral Image Generation Algorithm on Multi-core System.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2011

Real-Time Photo Sensor Dead Pixel Detection for Embedded Devices.
Proceedings of the 2011 International Conference on Digital Image Computing: Techniques and Applications (DICTA), 2011

System-level design exploration for 3-D stacked memory architectures.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Low-Power System Design for MPEG-2/4 AAC Audio Decoder Using Pure ASIC Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 1.4 MHz 0.21 mW MPEG-2/4 AAC single chip decoder.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards.
J. Signal Process. Syst., 2008

VLIW-aware software optimization of AAC decoder on parallel architecture core DSP (PACDSP) processor.
IEEE Trans. Consumer Electron., 2008

Optimization techniques of AAC decoder on PACDSP VLIW processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A Configurable Common Filterbank Processor for Multi-Standard Audio Decoder.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Hardware/Software Co-Design of MP3 Audio Decoder.
J. VLSI Signal Process., 2005

A hardware/software co-design case study on MPEG AAC audio decoder.
Int. J. Embed. Syst., 2005

SoC platform based design of MPEG-2/4 AAC audio decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A low power VLSI implementation for variable length decoder in MPEG-1 layer III.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003