Shing-Wu Tung

According to our database1, Shing-Wu Tung authored at least 17 papers between 1998 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 42.5µW/MHz ultra-low power 32-bit microcontroller - SPARK.
Proceedings of the 9th International Conference on Information, 2013

2012
A power management technology for mobile embedded system.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Low power and high performance 3-D multimedia platform.
Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

2011
Low power design and dynamic power management system for VLIW DSP subsystem.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

2003
Automatic interconnection rectification for SoC design verification based on the port order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

SoC design integration by using automatic interconnection rectification.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An automatic interconnection rectification technique for SoC design integration.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

On automatic-verification pattern generation for SoC withport-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001
ELITE Design Methodology of Foundation IP for Improving Synthesis Quality.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

An AVPG for SOC design verification with port order fault model.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1998
A Logical Fault Model for Library Coherence Checking.
J. Inf. Sci. Eng., 1998

Verification Pattern Generation for Core-Based Design Using Port Order Fault Model.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998


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