Chi-Hung Lin

According to our database1, Chi-Hung Lin authored at least 45 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Redundancy-Driven Multi-Task Adaptive Backstepping Tracking Control for Aerial Manipulators.
IEEE Access, 2024

2019
Energy Efficient Fog RAN (F-RAN) with Flexible BBU Resource Assignment for Latency Aware Mobile Edge Computing (MEC) Services.
Proceedings of the 90th IEEE Vehicular Technology Conference, 2019

2018
A 16b 6GS/S nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Soft Methodology for Cost-and-error Sensitive Classification.
CoRR, 2017

2016
Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Practical ILP-based routing of standard cells.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2014
Multi-core system performance prediction and analysis at the ESL.
Int. J. Comput. Sci. Eng., 2014

20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
Low power 3-D stacking multimedia platform with reconfigurable memory architecture.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012
IGDB.NSCLC: integrated genomic database of non-small cell lung cancer.
Nucleic Acids Res., 2012

Critical Factors Influencing Hospitals' Adoption of HL7 Version 2 Standards: An Empirical Investigation.
J. Medical Syst., 2012

Barriers to Physicians' Adoption of Healthcare Information Technology: An Empirical Study on Multiple Hospitals.
J. Medical Syst., 2012

Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC.
Proceedings of the IEEE 25th International SOC Conference, 2012

A simple methodology for soft cost-sensitive classification.
Proceedings of the 18th ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, 2012

Low power and high performance 3-D multimedia platform.
Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

2011
IGRhCellID: integrated genomic resources of human cell lines for identification.
Nucleic Acids Res., 2011

An Application of the Wireless Sensor Network Technology for Foehn Monitoring in Real Time.
Proceedings of the Ubiquitous Intelligence and Computing - 8th International Conference, 2011

A low-complexity SLM approach based on time-domain sub-block conversion matrices for OFDM PAPR reduction.
Proceedings of the 16th IEEE Symposium on Computers and Communications, 2011

Energy-Efficient Visual Eyes System for Wildlife.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

System-level design exploration for 3-D stacked memory architectures.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Cost-Sensitive Classification on Pathogen Species of Bacterial Meningitis by Surface Enhanced Raman Scattering.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2011

2010
Collaborative voltage scaling with online STA and variable-latency datapath.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Hybrid SVM/CART classification of pathogenic species of bacterial meningitis with surface-enhanced Raman scattering.
Proceedings of the 2010 IEEE International Conference on Bioinformatics and Biomedicine, 2010

2009
A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009

A fully integrated 2×2 MIMO dual-band dual- mode direct-conversion CMOS transceiver for WiMAX/WLAN applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Signature Evaluation Tool (SET): a Java-based tool to evaluate and visualize the sample discrimination abilities of gene expression signatures.
BMC Bioinform., 2008

easyExon - A Java-based GUI tool for processing and visualization of Affymetrix exon array data.
BMC Bioinform., 2008

2007
An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration.
Proceedings of the 44th Design Automation Conference, 2007

Configurable AMBA On-Chip Real-Time Signal Tracer.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
ArrayFusion: a web application for multi-dimensional analysis of CGH, SNP and microarray data.
Bioinform., 2006

2004
A 21-mW 8-b 125-MSample/s ADC in 0.09-mm<sup>2</sup> 0.13-μm CMOS.
IEEE J. Solid State Circuits, 2004

Sub-Microfabrication of Protein Micropatterns for Cell Biology Applications.
Proceedings of the 2004 International Conference on MEMS, 2004

2001
Wavelet based active contour model for object tracking.
Proceedings of the 2001 International Conference on Image Processing, 2001

1999
Operational Transconductance Amplifiers.
Proceedings of the VLSI Handbook., 1999

A single-chip universal cable set-top box/modem transceiver.
IEEE J. Solid State Circuits, 1999

A 2 V 5th-order fully-differential CMOS Gm-C filter for wideband communication.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A 5 MHz Nyquist rate continuous-time sigma-delta modulator for wideband wireless communication.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Design and analysis of an ultra low-voltage CMOS class-AB V-I converter for dynamic range enhancement.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Synthesis and analysis of high-order cascaded continuous-time ΣΔ modulators.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A 1.8V High Dynamic-Range CMOS High-Speed Four Quadrant Multiplier.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
A 10-b, 500-MSample/s CMOS DAC in 0.6 mm<sup>2</sup>.
IEEE J. Solid State Circuits, 1998

A Low-Voltage CMOS Exponential Function Circuit for AGC Applications.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

A low-voltage low-power CMOS V-I converter with rail-to-rail differential input for filtering applications.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A 1.8 V low-power CMOS high-speed four quadrant multiplier with rail-to-rail differential input.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


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