Chung-Hsiang Lin

According to our database, Chung-Hsiang Lin authored at least 7 papers between 2006 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support.

Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2015

SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs.

Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang

ACM Trans. Archit. Code Optim., 2015

2012

SECRET: Selective error correction for refresh energy reduction in DRAMs.

Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2010

Memory Latency Reduction via Thread Throttling.

Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009

Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.

Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin

ACM Trans. Design Autom. Electr. Syst., 2009

PPT: joint performance/power/thermal management of DRAM memory for multi-core systems.

Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2006

Hierarchical value cache encoding for off-chip data bus.

Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006