Yi-Jung Chen

According to our database1, Yi-Jung Chen authored at least 18 papers between 2004 and 2020.

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Bibliography

2020
Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories.
Proceedings of the SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30, 2020

2018
Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories.
Proceedings of the 2018 Conference on Research in Adaptive and Convergent Systems, 2018

2017
Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives.
IEEE Trans. Computers, 2017

Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture.
IEEE Access, 2017

2015
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs.
ACM Trans. Archit. Code Optim., 2015

Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs.
Proceedings of the 2015 Conference on research in adaptive and convergent systems, 2015

2014
Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
SECRET: Selective error correction for refresh energy reduction in DRAMs.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems.
IEEE Trans. Computers, 2011

2010
PM-COSYN: PE and memory co-synthesis for MPSoCs.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design.
J. Syst. Archit., 2009

2007
Improved Modulo (2n+1) Multiplier for IDEA.
J. Inf. Sci. Eng., 2007

An architectural co-synthesis algorithm for energy-aware network-on-chip design.
Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

Cache leakage control mechanism for hard real-time systems.
Proceedings of the 2007 International Conference on Compilers, 2007

2006
Branch Behavior Characterization for Multimedia Applications.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2004
A New Modulo (2<sup>n</sup>+1) Multiplier for IDEA.
Proceedings of the International Conference on Security and Management, 2004


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