Ciaran J. Brennan

According to our database1, Ciaran J. Brennan authored at least 4 papers between 2004 and 2007.

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Bibliography

2007
Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs.
Microelectron. Reliab., 2007

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs.
Microelectron. Reliab., 2007

2004
Power network analysis for ESD robustness in a 90nm ASIC design system.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

BIST controlled variable sense amp timing for 90nm embedded SRAM.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004


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