Kiran V. Chatty

According to our database1, Kiran V. Chatty authored at least 8 papers between 2003 and 2010.

Collaborative distances :
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2010
Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology.
Microelectronics Reliability, 2010

2009
Reliability aspects of gate oxide under ESD pulse stress.
Microelectronics Reliability, 2009

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology.
Microelectronics Reliability, 2009

2007
Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs.
Microelectronics Reliability, 2007

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs.
Microelectronics Reliability, 2007

2006
Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant.
Microelectronics Reliability, 2006

2003
Latchup Analysis Using Emission Microscopy.
Microelectronics Reliability, 2003

Optical and Electrical Testing of Latchup in I/O Interface Circuits.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003


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