Robert Gauthier

Affiliations:

IBM Microelectronics, Essex Junction, Semiconductor Research and Development Center, Systems and Technology Group, VT, USA

According to our database¹, Robert Gauthier authored at least 16 papers between 2003 and 2021.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2021

Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp.

[BibT_eX]

[DOI]

Sagar Premnath Karalkar

Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020

Understanding ESD Induced Thermal Mechanism in FinFETs Through Predictive TCAD Simulation.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology.

[BibT_eX]

[DOI]

Kyong Jin Hwang

Sagar Premnath Karalkar

Vishal Ganesan

Sevashanmugam Marimuthu

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies.

[BibT_eX]

[DOI]

You Li

Meng Miao

Robert Gauthier

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

A Novel HV-NPN ESD Protection Device with Buried Floating P-Type Implant.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2019

2017

Investigation of diode triggered silicon control rectifier turn-on time during ESD events.

[BibT_eX]

[DOI]

Ahmed Y. Ginawi

Robert Gauthier

Tian Xia

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2014

Reducing the turn-on time and overshoot voltage for a diode-triggered silicon-controlled rectifier during an electrostatic discharge event.

[BibT_eX]

[DOI]

Ahmed Ginawi

Tian Xia

Robert Gauthier

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2010

Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2010

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Reliability aspects of gate oxide under ESD pulse stress.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2009

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology.

[BibT_eX]

[DOI]

David Alvarez

Kiran V. Chatty

Christian Russ

Michel J. Abou-Khalil

Microelectron. Reliab., 2009

2007

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2007

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2007

2006

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant.

[BibT_eX]

[DOI]

David Alvarez

Michel J. Abou-Khalil

Microelectron. Reliab., 2006

2003

Latchup Analysis Using Emission Microscopy.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2003

Optical and Electrical Testing of Latchup in I/O Interface Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Robert Gauthier

Timeline

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