Joseph N. Kozhaya

According to our database, Joseph N. Kozhaya authored at least 14 papers between 1997 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

Pacman: driving nonuniform clock grid loads for low-skew robust clock network.

Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

2012

Subtractive Router for Tree-Driven-Grid Clocks.

Haifeng Qian, Phillip J. Restle, Joseph N. Kozhaya, Clifford L. Gunion

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus.

Joseph N. Kozhaya, Phillip J. Restle, Haifeng Qian

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2008

Power supply noise aware workload assignment for multi-core systems.

Aida Todri, Malgorzata Marek-Sadowska, Joseph N. Kozhaya

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2004

A chip-level electrostatic discharge simulation strategy.

Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

An electrically robust method for placing power gating switches in voltage islands.

Joseph N. Kozhaya, Luay Bakir

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Power network analysis for ESD robustness in a 90nm ASIC design system.

Ciaran J. Brennan, Joseph N. Kozhaya, Robert A. Proctor

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002

A multigrid-like technique for power grid analysis.

Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001

Analysis and Design of Power and Ground Networks for VLSI Circuits

Joseph N. Kozhaya

PhD thesis, 2001

Power estimation for large sequential circuits.

Joseph N. Kozhaya, Farid N. Najm

IEEE Trans. Very Large Scale Integr. Syst., 2001

I/O buffer placement methodology for ASICs.

Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Multi-grid methods for power grid simulation.

Sani R. Nassif, Joseph N. Kozhaya

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Fast power grid simulation.

Sani R. Nassif, Joseph N. Kozhaya

Proceedings of the 37th Conference on Design Automation, 2000

1997

Accurate power estimation for large sequential circuits.

Joseph N. Kozhaya, Farid N. Najm

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997