Roberto Airoldi
According to our database1,
Roberto Airoldi
authored at least 29 papers
between 2008 and 2017.
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Bibliography
2017
FPGA Implementation Issues of a Flexible Synchronizer Suitable for NC-OFDM-Based Cognitive Radios.
J. Syst. Archit., 2017
2016
HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms.
J. Signal Process. Syst., 2016
2015
Design and Implementation of a Power-aware FFT Core for OFDM-based DSA-enabled Cognitive Radios.
J. Signal Process. Syst., 2015
2014
EURASIP J. Adv. Signal Process., 2014
Design of a Flexible, Energy Efficient (Auto)Correlator Block for Timing Synchronization.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
2013
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Design & implementation of software defined radios on a homogeneous multi-processor architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
2012
Energy and power estimation of Coarse-Grain Reconfigurable Array based Fast Fourier Transform accelerators.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression.
Proceedings of the 2012 International Symposium on System on Chip, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
2011
J. Signal Process. Syst., 2011
Improving Reconfigurable Hardware Energy Efficiency and Robustness via DVFS-Scaled Homogeneous MP-SoC.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
2010
IEEE Micro, 2010
Int. J. Embed. Real Time Commun. Syst., 2010
Implementation of Conditional Execution on a Coarse-Grain Reconfigurable Array.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
Timing Synchronization for a Multi-Standard Receiver on a Multi-Processor System-onChip.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the 39th International Conference on Parallel Processing, 2010
2009
Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management.
Proceedings of the Embedded Computer Systems: Architectures, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008