Valerio Guarnieri

According to our database1, Valerio Guarnieri authored at least 20 papers between 2008 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
Code Manipulation for Virtual Platform Integration.
IEEE Trans. Computers, 2016

2015
A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.
Sensors, 2015

Reusing RTL Assertion Checkers for Verification of SystemC TLM Models.
J. Electron. Test., 2015

2014
Testbench Qualification of SystemC TLM Protocols through Mutation Analysis.
IEEE Trans. Computers, 2014

On the reuse of RTL assertions in SystemC TLM verification.
Proceedings of the 15th Latin American Test Workshop, 2014

A cross-level verification methodology for digital IPs augmented with embedded timing monitors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012
On the Reuse of TLM Mutation Analysis at RTL.
J. Electron. Test., 2012

FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction.
J. Electron. Test., 2012

HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels.
Des. Autom. Embed. Syst., 2012

Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis.
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

Energy aware TLM platform simulation via RTL abstraction.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

From RTL IP to functional system-level models with extra-functional properties.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Reduced-Complexity Transition-Fault Test Generation for Non-scan Circuits through High-Level Mutant Injection.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Mutation analysis for SystemC designs at TLM.
Proceedings of the 12th Latin American Test Workshop, 2011

Efficient implementation and abstraction of systemc data types for fast simulation.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction.
Proceedings of the 16th European Test Symposium, 2011

2010
Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2008
An optimized CLP-based technique for generating propagation sequences.
Proceedings of the 2008 East-West Design & Test Symposium, 2008


  Loading...