Giuseppe Di Guglielmo

According to our database1, Giuseppe Di Guglielmo authored at least 40 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Design and Implementation of a Dynamic Information Flow Tracking Architecture to Secure a RISC-V Core for IoT Applications.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

2017
COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators.
ACM Trans. Embedded Comput. Syst., 2017

System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Broadening the exploration of the accelerator design space in embedded scalable platforms.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2016
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems.
Proceedings of the 53rd Annual Design Automation Conference, 2016

On the design of scalable and reusable accelerators for big data applications.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip.
Proceedings of the 2016 International Conference on Compilers, 2016

High-level synthesis of accelerators in embedded scalable platforms.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
An Analysis of Accelerator Coupling in Heterogeneous Architectures.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

System-level memory optimization for high-level synthesis of component-based SoCs.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013
On the integration of model-driven design and dynamic assertion-based verification for embedded software.
Journal of Systems and Software, 2013

Efficient fault simulation through dynamic binary translation for dependability analysis of embedded software.
Proceedings of the 18th IEEE European Test Symposium, 2013

Automatic generation of compact formal properties for effective error detection.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012
Time-Constraint-Aware Optimization of Assertions in Embedded Software.
J. Electronic Testing, 2012

On the Reuse of TLM Mutation Analysis at RTL.
J. Electronic Testing, 2012

Accurate profiling of oracles for self-checking time-constrained embedded software.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Combining dynamic slicing and mutation operators for ESL correction.
Proceedings of the 17th IEEE European Test Symposium, 2012

On the use of assertions for embedded-software dynamic verification.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Enabling dynamic assertion-based verification of embedded software through model-driven design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A testbench specification language for SystemC verification.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Dynamic property mining for embedded software.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs.
J. Electronic Testing, 2011

EFSM-based model-driven approach to concolic testing of system-level design.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Model-driven design and validation of embedded software.
Proceedings of the 6th International Workshop on Automation of Software Test, 2011

Interactive presentation abstract: Assertion-based verification in embedded-software design.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Optimization of Assertion Placement in Time-Constrained Embedded Systems.
Proceedings of the 16th European Test Symposium, 2011

2010
HIFSuite: Tools for HDL Code Conversion and Manipulation.
EURASIP J. Emb. Sys., 2010

Semi-formal functional verification by EFSM traversing via NuSMV.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

HIFSuite: Tools for HDL code conversion and manipulation.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

RTOS-aware refinement for TLM2.0-based HW/SW designs.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
On the Functional Qualification of a Platform Model.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

The impact of EFSM composition on functional ATPG.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008
The role of parallel simulation in functional verification.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

2007
Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM.
IET Computers & Digital Techniques, 2007

2006
Improving Gate-Level ATPG by Traversing Concurrent EFSMs.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

EFSM Manipulation to Increase High-Level ATPG Effectiveness.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

FATE: a Functional ATPG to Traverse Unstabilized EFSMs.
Proceedings of the 11th European Test Symposium, 2006

2005
A Pseudo-Deterministic Functional ATPG based on EFSM Traversing.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005


  Loading...