Giuseppe Di Guglielmo
Orcid: 0000-0002-5749-1432
According to our database1,
Giuseppe Di Guglielmo
authored at least 73 papers
between 2005 and 2024.
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Bibliography
2024
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Low latency optical-based mode tracking with machine learning deployed on FPGAs on a tokamak.
CoRR, 2023
2022
<i>AIgean</i>: An Open Framework for Deploying Machine Learning on Heterogeneous Clusters.
ACM Trans. Reconfigurable Technol. Syst., 2022
Real-Time Inference With 2D Convolutional Neural Networks on Field Programmable Gate Arrays for High-Rate Particle Imaging Detectors.
Frontiers Artif. Intell., 2022
Frontiers Big Data, 2022
2021
Compressing deep neural networks on FPGAs to binary and ternary precision with hls4ml.
Mach. Learn. Sci. Technol., 2021
Mach. Learn. Sci. Technol., 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
IEEE Embed. Syst. Lett., 2021
A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHC.
CoRR, 2021
hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices.
CoRR, 2021
Proceedings of the 42nd IEEE Symposium on Security and Privacy, 2021
Proceedings of the Neural Information Processing Systems Track on Datasets and Benchmarks 1, 2021
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021
2020
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle Reconstruction in High Energy Physics.
Frontiers Big Data, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Proceedings of the Workshop on Computer Architecture Education, 2019
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design.
Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019
2018
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Design and Implementation of a Dynamic Information Flow Tracking Architecture to Secure a RISC-V Core for IoT Applications.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018
2017
COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators.
ACM Trans. Embed. Comput. Syst., 2017
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Broadening the exploration of the accelerator design space in embedded scalable platforms.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017
2016
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip.
Proceedings of the 2016 International Conference on Compilers, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
2013
On the integration of model-driven design and dynamic assertion-based verification for embedded software.
J. Syst. Softw., 2013
Efficient fault simulation through dynamic binary translation for dependability analysis of embedded software.
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
2012
J. Electron. Test., 2012
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Enabling dynamic assertion-based verification of embedded software through model-driven design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs.
J. Electron. Test., 2011
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011
Proceedings of the 6th International Workshop on Automation of Software Test, 2011
Interactive presentation abstract: Assertion-based verification in embedded-software design.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011
Proceedings of the 16th European Test Symposium, 2011
2010
EURASIP J. Embed. Syst., 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
2007
Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM.
IET Comput. Digit. Tech., 2007
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 11th European Test Symposium, 2006
2005
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005