Cynthia Sturton

Orcid: 0000-0003-3930-7440

According to our database1, Cynthia Sturton authored at least 32 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Isadora: automated information-flow property generation for hardware security verification.
J. Cryptogr. Eng., November, 2023

Impact of Emerging Hardware on Security and Privacy.
IEEE Secur. Priv., 2023

Augmented Symbolic Execution for Information Flow in Hardware Designs.
CoRR, 2023

Countering the Path Explosion Problem in the Symbolic Execution of Hardware Designs.
CoRR, 2023

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

SEIF: Augmented Symbolic Execution for Information Flow in Hardware Designs.
Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy, 2023

Sylvia: Countering the Path Explosion Problem in the Symbolic Execution of Hardware Designs.
Proceedings of the Formal Methods in Computer-Aided Design, 2023

2022
Toward Hardware Security Property Generation at Scale.
IEEE Secur. Priv., 2022

Automating hardware security property generation: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
End-to-End Automated Exploit Generation for Processor Security Validation.
IEEE Des. Test, 2021

A Methodology For Creating Information Flow Specifications of Hardware Designs.
CoRR, 2021

Isadora: Automated Information Flow Property Generation for Hardware Designs.
Proceedings of the ASHES@CCS 2021: Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security, 2021

2020
Transys: Leveraging Common Security Properties Across Hardware Designs.
Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020

Evaluating a Specification for its Support of Mode Awareness using Discrete and Continuous Model Checking.
Proceedings of the 23rd IEEE International Conference on Intelligent Transportation Systems, 2020

Evaluating Security Specification Mining for a CISC Architecture.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

2019
FinalFilter: Asserting Security Properties of a Processor at Runtime.
IEEE Micro, 2019

2018
Mining Security Critical Linear Temporal Logic Specifications for Processors.
Proceedings of the 19th International Workshop on Microprocessor and SOC Test and Verification, 2018

End-to-End Automated Exploit Generation for Validating the Security of Processor Designs.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

On Using Drivers' Eyes to Predict Accident-Causing Drowsiness Levels.
Proceedings of the 21st International Conference on Intelligent Transportation Systems, 2018

2017
A System to Verify Network Behavior of Known Cryptographic Clients.
Proceedings of the 14th USENIX Symposium on Networked Systems Design and Implementation, 2017

Identifying Security Critical Properties for the Dynamic Verification of a Processor.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Server-side verification of client behavior in cryptographic protocols.
CoRR, 2016

Model checking to find vulnerabilities in an instruction set architecture.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

2015
Usability of Augmented Reality for Revealing Secret Messages to Users but Not Their Devices.
Proceedings of the Eleventh Symposium On Usable Privacy and Security, 2015

SPECS: A Lightweight Runtime Mechanism for Protecting Software from Security-Critical Processor Bugs.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2013
Secure Virtualization with Formal Methods.
PhD thesis, 2013

Symbolic software model validation.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

2012
Automated Analysis of Election Audit Logs.
Proceedings of the 2012 Electronic Voting Technology Workshop / Workshop on Trustworthy Elections, 2012

Verification with small and short worlds.
Proceedings of the Formal Methods in Computer-Aided Design, 2012

2011
Defeating UCI: Building Stealthy and Malicious Hardware.
Proceedings of the 32nd IEEE Symposium on Security and Privacy, 2011

2009
Weight, Weight, Don't Tell Me: Using Scales to Select Ballots for Auditing.
Proceedings of the 2009 Electronic Voting Technology Workshop / Workshop on Trustworthy Elections, 2009

On voting machine design for verification and testability.
Proceedings of the 2009 ACM Conference on Computer and Communications Security, 2009


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