Farimah Farahmandi

Orcid: 0000-0003-1535-0938

According to our database1, Farimah Farahmandi authored at least 100 papers between 2013 and 2024.

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Bibliography

2024
TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024

SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024

Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM.
ACM Trans. Design Autom. Electr. Syst., January, 2024

AGILE: Automated Assertion Generation to Detect Information Leakage Vulnerabilities.
IEEE Trans. Inf. Forensics Secur., 2024

Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An Exploration.
IEEE Trans. Inf. Forensics Secur., 2024

INSPECT: Investigating Supply Chain and Cyber-Physical Security of Battery Systems.
IACR Cryptol. ePrint Arch., 2024

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration.
IEEE Access, 2024

CAD Tools Pathway in Hardware Security.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations.
IEEE Des. Test, October, 2023

HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology.
IEEE Des. Test, April, 2023

Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle.
ACM J. Emerg. Technol. Comput. Syst., January, 2023

A Comprehensive Survey on Non-Invasive Fault Injection Attacks.
IACR Cryptol. ePrint Arch., 2023

LLM for SoC Security: A Paradigm Shift.
IACR Cryptol. ePrint Arch., 2023

ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction.
IACR Cryptol. ePrint Arch., 2023

ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach.
IEEE Access, 2023

CAPEC: A Cellular Automata Guided FSM-based IP Authentication Scheme.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Security of Hardware Generators: Enabling Assurance in High-Level Synthesis.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Benchmarking of SoC-Level Hardware Vulnerabilities: A Complete Walkthrough.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering.
Proceedings of the IEEE European Test Symposium, 2023

PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates.
Proceedings of the IEEE European Test Symposium, 2023

QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

RTLock: IP Protection using Scan-Aware Logic Locking at RTL.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SheLL: Shrinking eFPGA Fabrics for Logic Locking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

ActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

SecHLS: Enabling Security Awareness in High-Level Synthesis.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

SHarPen: SoC Security Verification by Hardware Penetration Test.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level.
IEEE Trans. Very Large Scale Integr. Syst., 2022

eChain: A Blockchain-Enabled Ecosystem for Electronic Device Authenticity Verification.
IEEE Trans. Consumer Electron., 2022

SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Analyzing Security Vulnerabilities Induced by High-level Synthesis.
ACM J. Emerg. Technol. Comput. Syst., 2022

ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance.
IACR Cryptol. ePrint Arch., 2022

Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications.
IACR Cryptol. ePrint Arch., 2022

PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms.
IACR Cryptol. ePrint Arch., 2022

Advances in Logic Locking: Past, Present, and Prospects.
IACR Cryptol. ePrint Arch., 2022

Secure Physical Design.
IACR Cryptol. ePrint Arch., 2022

Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions.
IACR Cryptol. ePrint Arch., 2022

Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs.
IACR Cryptol. ePrint Arch., 2022

FSMx: Finite State Machine Extraction from Flattened Netlist With Application to Security.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications.
Proceedings of the IEEE International Test Conference, 2022

ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features.
Proceedings of the IEEE International Test Conference, 2022

LDTFI: Layout-aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Security Properties Driven Pre-Silicon Laser Fault Injection Assessment.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

FTC: A Universal Sensor for Fault Injection Attack Detection.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

AIME: Watermarking AI Models by Leveraging Errors.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

O'clock: lock the clock via clock-gating for SoC IP protection.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Secure by construction: addressing security vulnerabilities introduced during high-level synthesis: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks.
ACM Trans. Design Autom. Electr. Syst., 2021

An End-to-End Bitstream Tamper Attack Against Flip-Chip FPGAs.
IACR Cryptol. ePrint Arch., 2021

What is All the FaaS About? - Remote Exploitation of FPGA-as-a-Service Platforms.
IACR Cryptol. ePrint Arch., 2021

SoC Security Properties and Rules.
IACR Cryptol. ePrint Arch., 2021

Quantifiable Assurance: From IPs to Platforms.
IACR Cryptol. ePrint Arch., 2021

SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

SymbA: Symbolic Execution at C-level for Hardware Trojan Activation.
Proceedings of the IEEE International Test Conference, 2021

LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment.
Proceedings of the IEEE International Test Conference, 2021

HEXON: Protecting Firmware Using Hardware-Assisted Execution-Level Obfuscation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Secure High-Level Synthesis: Challenges and Solutions.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Required Policies and Properties of the Security Engine of an SoC.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

POCA: First Power-on Chip Authentication in Untrusted Foundry and Assembly.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

BOFT: Exploitable Buffer Overflow Detection by Information Flow Tracking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Invited: End-to-End Secure SoC Lifecycle Management.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

HLock: Locking IPs at the High-Level Language.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation.
ACM Trans. Design Autom. Electr. Syst., 2020

Defense-in-depth: A recipe for logic locking to prevail.
Integr., 2020

SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

SPARTA: A Laser Probing Approach for Trojan Detection.
Proceedings of the IEEE International Test Conference, 2020

Design Obfuscation versus Test.
Proceedings of the IEEE European Test Symposium, 2020

2019
Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits.
IEEE Trans. Computers, 2019

Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design.
IACR Cryptol. ePrint Arch., 2019

SoC Security Verification using Property Checking.
Proceedings of the IEEE International Test Conference, 2019

FPGA Bitstream Security: A Day in the Life.
Proceedings of the IEEE International Test Conference, 2019

Security and Trust Verification of IoT SoCs.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
Hardware Trojan Detection Using ATPG and Model Checking.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution.
Proceedings of the IEEE International Test Conference, 2018

Directed test generation using concolic testing on RTL models.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
FSM Anomaly Detection Using Formal Analysis.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Cost-effective analysis of post-silicon functional coverage events.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Trojan localization using symbolic algebra.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Exploiting transaction level models for observability-aware post-silicon test generation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Automated test generation for Debugging arithmetic circuits.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction.
Microprocess. Microsystems, 2015

Pre-silicon security verification and validation: a formal perspective.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2013
A new structure for interconnect offline testing.
Proceedings of the East-West Design & Test Symposium, 2013


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