Cyril Chevalier

According to our database1, Cyril Chevalier authored at least 9 papers between 1993 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality.
J. Low Power Electron., 2017

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization.
J. Circuits Syst. Comput., 2017

2016
A Hybrid Power Estimation Technique to improve IP power models quality.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

A hybrid power modeling approach to enhance high-level power models.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
A generic clock controller for low power systems: Experimentation on an AXI bus.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

An efficient hybrid power modeling approach for accurate gate-level power estimation.
Proceedings of the 27th International Conference on Microelectronics, 2015

2014
Distributed asynchronous controllers for clock management in low power systems.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

1995
BIST hardware generator for mixed test scheme.
Proceedings of the 1995 European Design and Test Conference, 1995

1993
LFSROM an algorithm for automatic design synthesis of hardware test pattern generator.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993


  Loading...