Alberto Bosio

According to our database1, Alberto Bosio authored at least 206 papers between 2005 and 2022.

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Bibliography

2022
Guest Editorial: Computation-In-Memory (CIM): from Device to Applications.
ACM J. Emerg. Technol. Comput. Syst., 2022

Hitless memory-reconfigurable photonic reservoir computing architecture.
CoRR, 2022

Reliability assessment of FreeRTOS in Embedded Systems.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022

Selective Hardening of Critical Neurons in Deep Neural Networks.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

A Design Space Exploration Framework for Memristor-Based Crossbar Architecture.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

A Heuristic Exploration of Retraining-free Weight-Sharing for CNN Compression.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Input-Aware Approximate Computing.
Proceedings of the IEEE International Conference on Automation, 2022

2021
Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms.
Future Gener. Comput. Syst., 2021

Fast Exploration of Weight Sharing Opportunities for CNN Compression.
CoRR, 2021

Multi-Objective Application-Driven Approximate Design Method.
IEEE Access, 2021

Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Approximate Computing for Safety-Critical Applications.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability<sup>*</sup>.
Proceedings of the 26th IEEE European Test Symposium, 2021

Tutorial: Silicon Systems for Wireless LAN.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

AdequateDL: Approximating Deep Learning Accelerators.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Efficient Neural Network Approximation via Bayesian Reasoning.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

A Model-Based Framework to Assess the Reliability of Safety-Critical Applications.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Emerging Technologies: Challenges and Opportunities for Logic Synthesis.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020
A Survey of Testing Techniques for Approximate Integrated Circuits.
Proc. IEEE, 2020

A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns.
Proceedings of the IEEE International Test Conference, 2020

Learning-Based Cell-Aware Defect Diagnosis of Customer Returns.
Proceedings of the IEEE European Test Symposium, 2020

Design, Verification, Test and In-Field Implications of Approximate Computing Systems.
Proceedings of the IEEE European Test Symposium, 2020

Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Cross-Layer Soft-Error Resilience Analysis of Computing Systems.
Proceedings of the 50th Annual IEEE-IFIP International Conference on Dependable Systems and Networks, 2020

Evaluating Convolutional Neural Networks Reliability depending on their Data Representation.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

A Pipelined Multi-Level Fault Injector for Deep Neural Networks.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

On the Analysis of Real-time Operating System Reliability in Embedded Systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

Maximizing Yield for Approximate Integrated Circuits.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Anytime Floating-Point Addition and Multiplication-Concepts and Implementations.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
IEEE Trans. Computers, 2019

Special Issue on Design, Technology, and Test of Integrated Circuits and Systems.
J. Circuits Syst. Comput., 2019

Assessing the Reliability of Successive Approximate Computing Algorithms under Fault Injection.
J. Electron. Test., 2019

Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems.
J. Electron. Test., 2019

Exploiting Approximate Computing to Increase System Lifetime.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Exploiting approximate computing for low-cost fault tolerant architectures.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

A Reliability Analysis of a Deep Neural Network.
Proceedings of the IEEE Latin American Test Symposium, 2019

International Symposium on Design and Diagnostics of Electronic Circuits and Systems.
Proceedings of the IEEE International Test Conference, 2019

Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Alternatives to Fault Injections for Early Safety/Security Evaluations.
Proceedings of the 24th IEEE European Test Symposium, 2019

Rebooting Computing: The Challenges for Test and Reliability.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
Scan-Chain Intra-Cell Aware Testing.
IEEE Trans. Emerg. Top. Comput., 2018

Estimating dynamic power consumption for memristor-based CiM architecture.
Microelectron. Reliab., 2018

Test and Reliability in Approximate Computing.
J. Electron. Test., 2018

Special session: How approximate computing impacts verification, test and reliability.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Testing approximate digital circuits: Challenges and opportunities.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs.
Proceedings of the IEEE International Test Conference, 2018

Predicting the Impact of Functional Approximation: from Component- to Application-Level.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Performances VS Reliability: how to exploit Approximate Computing for Safety-Critical applications.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Synthesis of Finite State Machines on Memristor Crossbars.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

ARFT: An Approximative Redundant Technique for Fault Tolerance.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Computing reliability: On the differences between software testing and software fault injection techniques.
Microprocess. Microsystems, 2017

A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality.
J. Low Power Electron., 2017

Microprocessor Testing: Functional Meets Structural Test.
J. Circuits Syst. Comput., 2017

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization.
J. Circuits Syst. Comput., 2017

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits.
J. Electron. Test., 2017

Approximate computing: Design & test for integrated circuits.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Reliability of computing systems: From flip flops to variables.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Towards digital circuit approximation by exploiting fault simulation.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

An effective fault-injection framework for memory reliability enhancement perspectives.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

Memristive devices: Technology, design automation and computing frontiers.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

Towards approximation during test of Integrated Circuits.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

Formal Design Space Exploration for memristor-based crossbar architecture.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
Design for Test and Diagnosis of Power Switches.
J. Circuits Syst. Comput., 2016

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores.
J. Electron. Test., 2016

Cache- and register-aware system reliability evaluation based on data lifetime analysis.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Thermal issues in test: An overview of the significant aspects and industrial practice.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

XbarGen: A memristor based boolean logic synthesis tool.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

A Hybrid Power Estimation Technique to improve IP power models quality.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Faster-than-at-speed execution of functional programs: An experimental analysis.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Cross-layer system reliability assessment framework for hardware faults.
Proceedings of the 2016 IEEE International Test Conference, 2016

Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

An effective BIST architecture for power-gating mechanisms in low-power SRAMs.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Analysis of setup and hold margins inside silicon for advanced technology nodes.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Cache-aware reliability evaluation through LLVM-based analysis and fault injection.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Test of low power circuits: Issues and industrial practices.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A low-cost susceptibility analysis methodology to selectively harden logic circuits.
Proceedings of the 21th IEEE European Test Symposium, 2016

Auto-adaptive ultra-low power IC.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

An effective approach for functional test programs compaction.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

A hybrid power modeling approach to enhance high-level power models.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

System-level reliability evaluation through cache-aware software-based fault injection.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.
Microprocess. Microsystems, 2015

An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

An efficient hybrid power modeling approach for accurate gate-level power estimation.
Proceedings of the 27th International Conference on Microelectronics, 2015

An effective hybrid fault-tolerant architecture for pipelined cores.
Proceedings of the 20th IEEE European Test Symposium, 2015

Scan-chain intra-cell defects grading.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Software testing and software fault injection.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

An effective ATPG flow for Gate Delay Faults.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Design-for-Diagnosis Architecture for Power Switches.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Exploring the impact of functional test programs re-used for power-aware testing.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Globally Constrained Locally Optimized 3-D Power Delivery Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2014

On the Test and Mitigation of Malfunctions in Low-Power SRAMs.
J. Electron. Test., 2014

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems.
J. Electron. Test., 2014

Intra-Cell Defects Diagnosis.
J. Electron. Test., 2014

TSV aware timing analysis and diagnosis in paths with multiple TSVs.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A Comprehensive Evaluation of Functional Programs for Power-Aware Test.
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

iBoX - Jitter based Power Supply Noise sensor.
Proceedings of the 19th IEEE European Test Symposium, 2014

A novel adaptive fault tolerant flip-flop architecture based on TMR.
Proceedings of the 19th IEEE European Test Symposium, 2014

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Test and diagnosis of power switches.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Timing-aware ATPG for critical paths with multiple TSVs.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

An intra-cell defect grading tool.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

On the Generation of Diagnostic Test Set for Intra-cell Defects.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A Study of Tapered 3-D TSVs for Power and Thermal Integrity.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption.
J. Low Power Electron., 2013

A built-in scheme for testing and repairing voltage regulators of low-power srams.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Characterization of an SRAM based particle detector for mixed-field radiation environments.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs.
Proceedings of the 2013 IEEE International Test Conference, 2013

A novel method to mitigate TSV electromigration for 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Effect-cause intra-cell diagnosis at transistor level.
Proceedings of the International Symposium on Quality Electronic Design, 2013

SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability.
Proceedings of the 18th IEEE European Test Symposium, 2013

Computing detection probability of delay defects in signal line tsvs.
Proceedings of the 18th IEEE European Test Symposium, 2013

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Test solution for data retention faults in low-power SRAMs.
Proceedings of the Design, Automation and Test in Europe, 2013

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Statistical Reliability Estimation of Microprocessor-Based Systems.
IEEE Trans. Computers, 2012

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC<sup>TM</sup> eFlash Memories.
J. Electron. Test., 2012

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes.
J. Electron. Test., 2012

A pseudo-dynamic comparator for error detection in fault tolerant architectures.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Advanced test methods for SRAMs.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low-power SRAMs power mode control logic: Failure analysis and test solutions.
Proceedings of the 2012 IEEE International Test Conference, 2012

Evaluation of test algorithms stress effect on SRAMs under neutron radiation.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Defect analysis in power mode control logic of low-power SRAMs.
Proceedings of the 17th IEEE European Test Symposium, 2012

Through-Silicon-Via resistive-open defect analysis.
Proceedings of the 17th IEEE European Test Symposium, 2012

Coupling-based resistive-open defects in TAS-MRAM architectures.
Proceedings of the 17th IEEE European Test Symposium, 2012

Impact of resistive-open defects on the heat current of TAS-MRAM architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Power Supply Noise Sensor Based on Timing Uncertainty Measurements.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Why and How Controlling Power Consumption during Test: A Survey.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Peak Power Estimation: A Case Study on CPU Cores.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Impact of Resistive-Bridge Defects in TAS-MRAM Architectures.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
On using address scrambling to implement defect tolerance in SRAMs.
Proceedings of the 2011 IEEE International Test Conference, 2011

A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.
Proceedings of the 16th European Test Symposium, 2011

Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

On the Modeling of Gate Delay Faults by Means of Transition Delay Faults.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

A study of path delay variations in the presence of uncorrelated power and ground supply noise.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

On using a SPICE-like TSTAC™ eFlash model for design and test.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Failure Analysis and Test Solutions for Low-Power SRAMs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Power-Aware Test Pattern Generation for At-Speed LOS Testing.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects.
IEEE Trans. Computers, 2010

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.
J. Low Power Electron., 2010

Detecting NBTI induced failures in SRAM core-cells.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Is test power reduction through X-filling good enough?
Proceedings of the 2011 IEEE International Test Conference, 2010

Parity prediction synthesis for nano-electronic gate designs.
Proceedings of the 2011 IEEE International Test Conference, 2010

A two-layer SPICE model of the ATMEL TSTAC<sup>TM</sup> eFlash memory technology for defect injection and faulty behavior prediction.
Proceedings of the 15th European Test Symposium, 2010

Setting test conditions for improving SRAM reliability.
Proceedings of the 15th European Test Symposium, 2010

Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.
Proceedings of the 15th European Test Symposium, 2010

Impact of Resistive-Bridging Defects in SRAM Core-Cell.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

An Exact and Efficient Critical Path Tracing Algorithm.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A statistical simulation method for reliability analysis of SRAM core-cells.
Proceedings of the 47th Design Automation Conference, 2010

A Memory Fault Simulator for Radiation-Induced Effects in SRAMs.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

A Comprehensive System-on-Chip Logic Diagnosis.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
A dynamic programming algorithm for the single-machine scheduling problem with release dates and deteriorating processing times.
Math. Methods Oper. Res., 2009

Is triple modular redundancy suitable for yield improvement?
IET Comput. Digit. Tech., 2009

Are IEEE-1500-Compliant Cores Really Compliant to the Standard?.
IEEE Des. Test Comput., 2009

NAND flash testing: A preliminary study on actual defects.
Proceedings of the 2009 IEEE International Test Conference, 2009

A case study on logic diagnosis for System-on-Chip.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An efficient fault simulation technique for transition faults in non-scan sequential circuits.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Comprehensive bridging fault diagnosis based on the SLAT paradigm.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Delay Fault Diagnosis in Sequential Circuits.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
March Test Generation Revealed.
IEEE Trans. Computers, 2008

SoC Yield Improvement: Redundant Architectures to the Rescue?
Proceedings of the 2008 IEEE International Test Conference, 2008

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs.
Proceedings of the 2008 IEEE International Test Conference, 2008

Yield Improvement, Fault-Tolerance to the Rescue?.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A Modular Memory BIST for Optimized Memory Repair.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Using TMR Architectures for Yield Improvement.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Improving Diagnosis Resolution without Physical Information.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

SoC Symbolic Simulation: a case study on delay fault testing.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

LIFTING: A Flexible Open-Source Fault Simulator.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs.
IET Comput. Digit. Tech., 2007

Automating the IEEE std.1500 compliance verification for embedded cores.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

DERRIC: A Tool for Unified Logic Diagnosis.
Proceedings of the 12th European Test Symposium, 2007

A Functional Verification Based Fault Injection Environment.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A Mixed Approach for Unified Logic Diagnosis.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
A dynamic programming algorithm for the single-machine scheduling problem with deteriorating processing times.
Electron. Notes Discret. Math., 2006

A 22n March Test for Realistic Static Linked Faults in SRAMs.
Proceedings of the 11th European Test Symposium, 2006

Automatic March Tests Generation for Multi-Port SRAMs.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Automatic march tests generations for static linked faults in SRAMs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
March AB, March AB1: new March tests for unlinked dynamic memory faults.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Automatic March tests generation for static and dynamic faults in SRAMs.
Proceedings of the 10th European Test Symposium, 2005


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