Alberto Bosio
Orcid: 0000-0001-6116-7339
According to our database1,
Alberto Bosio
authored at least 233 papers
between 2005 and 2024.
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Bibliography
2024
Guest Editorial IEEE Transactions on Emerging Topics in Special Section on Emerging In-Memory Computing Architectures and Applications.
IEEE Trans. Emerg. Top. Comput., 2024
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators.
CoRR, 2024
2023
ACM Trans. Embed. Comput. Syst., July, 2023
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems.
IEEE Des. Test, June, 2023
Computer, February, 2023
Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the International Conference on Microelectronics, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks.
IEEE Trans. Emerg. Top. Comput., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
Exploiting Approximate Computing for Efficient and Reliable Convolutional Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Proceedings of the IEEE International Conference on Automation, 2022
Proceedings of the Approximate Computing, 2022
2021
Investigating data representation for efficient and reliable Convolutional Neural Networks.
Microprocess. Microsystems, October, 2021
Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms.
Future Gener. Comput. Syst., 2021
Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability<sup>*</sup>.
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
2020
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the IEEE European Test Symposium, 2020
Design, Verification, Test and In-Field Implications of Approximate Computing Systems.
Proceedings of the IEEE European Test Symposium, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
Proceedings of the 50th Annual IEEE-IFIP International Conference on Dependable Systems and Networks, 2020
Evaluating Convolutional Neural Networks Reliability depending on their Data Representation.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020
2019
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
IEEE Trans. Computers, 2019
J. Circuits Syst. Comput., 2019
Assessing the Reliability of Successive Approximate Computing Algorithms under Fault Injection.
J. Electron. Test., 2019
Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems.
J. Electron. Test., 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
International Symposium on Design and Diagnostics of Electronic Circuits and Systems.
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
2018
Microelectron. Reliab., 2018
Special session: How approximate computing impacts verification, test and reliability.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the IEEE International Test Conference, 2018
Predicting the Impact of Functional Approximation: from Component- to Application-Level.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Performances VS Reliability: how to exploit Approximate Computing for Safety-Critical applications.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
Computing reliability: On the differences between software testing and software fault injection techniques.
Microprocess. Microsystems, 2017
J. Low Power Electron., 2017
J. Circuits Syst. Comput., 2017
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization.
J. Circuits Syst. Comput., 2017
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits.
J. Electron. Test., 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
An effective fault-injection framework for memory reliability enhancement perspectives.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017
2016
J. Electron. Test., 2016
Cache- and register-aware system reliability evaluation based on data lifetime analysis.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Thermal issues in test: An overview of the significant aspects and industrial practice.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
System-level reliability evaluation through cache-aware software-based fault injection.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
2015
Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.
Microprocess. Microsystems, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
An efficient hybrid power modeling approach for accurate gate-level power estimation.
Proceedings of the 27th International Conference on Microelectronics, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
J. Electron. Test., 2014
J. Electron. Test., 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption.
J. Low Power Electron., 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Characterization of an SRAM based particle detector for mixed-field radiation environments.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability.
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
IEEE Trans. Computers, 2012
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC<sup>TM</sup> eFlash Memories.
J. Electron. Test., 2012
J. Electron. Test., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Proceedings of the 2011 IEEE International Test Conference, 2011
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
A study of path delay variations in the presence of uncorrelated power and ground supply noise.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
IEEE Trans. Computers, 2010
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.
J. Low Power Electron., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
A two-layer SPICE model of the ATMEL TSTAC<sup>TM</sup> eFlash memory technology for defect injection and faulty behavior prediction.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 15th European Test Symposium, 2010
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
A dynamic programming algorithm for the single-machine scheduling problem with release dates and deteriorating processing times.
Math. Methods Oper. Res., 2009
IET Comput. Digit. Tech., 2009
IEEE Des. Test Comput., 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
An efficient fault simulation technique for transition faults in non-scan sequential circuits.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs.
IET Comput. Digit. Tech., 2007
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
A dynamic programming algorithm for the single-machine scheduling problem with deteriorating processing times.
Electron. Notes Discret. Math., 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 15th Asian Test Symposium, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 10th European Test Symposium, 2005