Patrick Girard

Affiliations:
  • University of Montpellier, LRIMM


According to our database1, Patrick Girard authored at least 273 papers between 1992 and 2022.

Collaborative distances:

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Bibliography

2022
Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments.
IEEE Trans. Emerg. Top. Comput., 2022

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications.
IEEE Trans. Aerosp. Electron. Syst., 2022

A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors.
Proceedings of the IEEE European Test Symposium, 2022

SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors.
IEEE Trans. Very Large Scale Integr. Syst., 2021

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories.
Proc. IEEE, 2021

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications.
Microelectron. J., 2021

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications.
J. Electron. Test., 2021

A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors.
Proceedings of the IEEE International Test Conference, 2021

Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular Automata.
Proceedings of the 26th IEEE European Test Symposium, 2021

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability<sup>*</sup>.
Proceedings of the 26th IEEE European Test Symposium, 2021

Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

A Learning-Based Methodology for Accelerating Cell-Aware Model Generation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets.
IEEE Trans. Circuits Syst., 2020

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment.
IEEE Trans. Computers, 2020

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications.
IEEE Trans. Aerosp. Electron. Syst., 2020

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications.
IEEE Trans. Aerosp. Electron. Syst., 2020

A Survey of Testing Techniques for Approximate Integrated Circuits.
Proc. IEEE, 2020

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits.
J. Electron. Test., 2020

A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns.
Proceedings of the IEEE International Test Conference, 2020

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors.
Proceedings of the IEEE International Test Conference in Asia, 2020

DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Impact of Aging on Soft Error Susceptibility in CMOS Circuits.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Learning-Based Cell-Aware Defect Diagnosis of Customer Returns.
Proceedings of the IEEE European Test Symposium, 2020

QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction.
Proceedings of the IEEE European Test Symposium, 2020

Design, Verification, Test and In-Field Implications of Approximate Computing Systems.
Proceedings of the IEEE European Test Symposium, 2020

Maximizing Yield for Approximate Integrated Circuits.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets.
IEEE Access, 2019

A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
Scan-Chain Intra-Cell Aware Testing.
IEEE Trans. Emerg. Top. Comput., 2018

A Special Section On Machine Learning and Artificial Intelligence In Low Power Electronics.
J. Low Power Electron., 2018

<i>A Special Section on</i> Industrial Experiences in Low Power Electronics.
J. Low Power Electron., 2018

<i>A Special Section on</i> Low Power Electronics: A Compilation of Emerging Ideas and Efficient Solutions.
J. Low Power Electron., 2018

Testing approximate digital circuits: Challenges and opportunities.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs.
Proceedings of the IEEE International Test Conference, 2018

Power-aware testing in the Era of IoT.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Is aproximate computing suitable for selective hardening of arithmetic circuits?
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality.
J. Low Power Electron., 2017

<i>A Special Section on</i> New and Future Trends in Low Power Electronics.
J. Low Power Electron., 2017

Microprocessor Testing: Functional Meets Structural Test.
J. Circuits Syst. Comput., 2017

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization.
J. Circuits Syst. Comput., 2017

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits.
J. Electron. Test., 2017

Approximate computing: Design & test for integrated circuits.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Towards digital circuit approximation by exploiting fault simulation.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

An effective fault-injection framework for memory reliability enhancement perspectives.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

Towards approximation during test of Integrated Circuits.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
Design for Test and Diagnosis of Power Switches.
J. Circuits Syst. Comput., 2016

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores.
J. Electron. Test., 2016

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization.
J. Electron. Test., 2016

A Hybrid Power Estimation Technique to improve IP power models quality.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

An effective BIST architecture for power-gating mechanisms in low-power SRAMs.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Test of low power circuits: Issues and industrial practices.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A low-cost susceptibility analysis methodology to selectively harden logic circuits.
Proceedings of the 21th IEEE European Test Symposium, 2016

Auto-adaptive ultra-low power IC.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

An effective approach for functional test programs compaction.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

A hybrid power modeling approach to enhance high-level power models.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

An efficient hybrid power modeling approach for accurate gate-level power estimation.
Proceedings of the 27th International Conference on Microelectronics, 2015

An effective hybrid fault-tolerant architecture for pipelined cores.
Proceedings of the 20th IEEE European Test Symposium, 2015

Scan-chain intra-cell defects grading.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

An effective ATPG flow for Gate Delay Faults.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Design-for-Diagnosis Architecture for Power Switches.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Exploring the impact of functional test programs re-used for power-aware testing.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Globally Constrained Locally Optimized 3-D Power Delivery Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2014

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
IEICE Trans. Inf. Syst., 2014

On the Test and Mitigation of Malfunctions in Low-Power SRAMs.
J. Electron. Test., 2014

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems.
J. Electron. Test., 2014

Intra-Cell Defects Diagnosis.
J. Electron. Test., 2014

TSV aware timing analysis and diagnosis in paths with multiple TSVs.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A Comprehensive Evaluation of Functional Programs for Power-Aware Test.
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

iBoX - Jitter based Power Supply Noise sensor.
Proceedings of the 19th IEEE European Test Symposium, 2014

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Test and diagnosis of power switches.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Timing-aware ATPG for critical paths with multiple TSVs.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

An intra-cell defect grading tool.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

On the Generation of Diagnostic Test Set for Intra-cell Defects.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A Study of Tapered 3-D TSVs for Power and Thermal Integrity.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption.
J. Low Power Electron., 2013

A built-in scheme for testing and repairing voltage regulators of low-power srams.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Characterization of an SRAM based particle detector for mixed-field radiation environments.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs.
Proceedings of the 2013 IEEE International Test Conference, 2013

A novel method to mitigate TSV electromigration for 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Effect-cause intra-cell diagnosis at transistor level.
Proceedings of the International Symposium on Quality Electronic Design, 2013

SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability.
Proceedings of the 18th IEEE European Test Symposium, 2013

Computing detection probability of delay defects in signal line tsvs.
Proceedings of the 18th IEEE European Test Symposium, 2013

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Test solution for data retention faults in low-power SRAMs.
Proceedings of the Design, Automation and Test in Europe, 2013

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing.
Proceedings of the 22nd Asian Test Symposium, 2013

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.
J. Low Power Electron., 2012

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC<sup>TM</sup> eFlash Memories.
J. Electron. Test., 2012

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk.
J. Electron. Test., 2012

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes.
J. Electron. Test., 2012

A pseudo-dynamic comparator for error detection in fault tolerant architectures.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Advanced test methods for SRAMs.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low-power SRAMs power mode control logic: Failure analysis and test solutions.
Proceedings of the 2012 IEEE International Test Conference, 2012

On pinpoint capture power management in at-speed scan test generation.
Proceedings of the 2012 IEEE International Test Conference, 2012

Evaluation of test algorithms stress effect on SRAMs under neutron radiation.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Defect analysis in power mode control logic of low-power SRAMs.
Proceedings of the 17th IEEE European Test Symposium, 2012

Through-Silicon-Via resistive-open defect analysis.
Proceedings of the 17th IEEE European Test Symposium, 2012

Coupling-based resistive-open defects in TAS-MRAM architectures.
Proceedings of the 17th IEEE European Test Symposium, 2012

Impact of resistive-open defects on the heat current of TAS-MRAM architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Power Supply Noise Sensor Based on Timing Uncertainty Measurements.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Why and How Controlling Power Consumption during Test: A Survey.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Peak Power Estimation: A Case Study on CPU Cores.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Impact of Resistive-Bridge Defects in TAS-MRAM Architectures.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Power-aware test generation with guaranteed launch safety for at-speed scan testing.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

On using address scrambling to implement defect tolerance in SRAMs.
Proceedings of the 2011 IEEE International Test Conference, 2011

A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.
Proceedings of the 16th European Test Symposium, 2011

Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

On the Modeling of Gate Delay Faults by Means of Transition Delay Faults.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

A study of path delay variations in the presence of uncorrelated power and ground supply noise.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

On using a SPICE-like TSTAC™ eFlash model for design and test.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Failure Analysis and Test Solutions for Low-Power SRAMs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Power-Aware Test Pattern Generation for At-Speed LOS Testing.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects.
IEEE Trans. Computers, 2010

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.
J. Low Power Electron., 2010

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.
IEICE Trans. Inf. Syst., 2010

Detecting NBTI induced failures in SRAM core-cells.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Is test power reduction through X-filling good enough?
Proceedings of the 2011 IEEE International Test Conference, 2010

Parity prediction synthesis for nano-electronic gate designs.
Proceedings of the 2011 IEEE International Test Conference, 2010

A roaming memory test bench for detecting particle induced SEUs.
Proceedings of the 2011 IEEE International Test Conference, 2010

Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A two-layer SPICE model of the ATMEL TSTAC<sup>TM</sup> eFlash memory technology for defect injection and faulty behavior prediction.
Proceedings of the 15th European Test Symposium, 2010

Setting test conditions for improving SRAM reliability.
Proceedings of the 15th European Test Symposium, 2010

Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.
Proceedings of the 15th European Test Symposium, 2010

Impact of Resistive-Bridging Defects in SRAM Core-Cell.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

An Exact and Efficient Critical Path Tracing Algorithm.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A statistical simulation method for reliability analysis of SRAM core-cells.
Proceedings of the 47th Design Automation Conference, 2010

A Memory Fault Simulator for Radiation-Induced Effects in SRAMs.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

A Comprehensive System-on-Chip Logic Diagnosis.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Analysis of Resistive-Open Defects in SRAM Sense Amplifiers.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Is triple modular redundancy suitable for yield improvement?
IET Comput. Digit. Tech., 2009

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash.
J. Electron. Test., 2009

NAND flash testing: A preliminary study on actual defects.
Proceedings of the 2009 IEEE International Test Conference, 2009

A case study on logic diagnosis for System-on-Chip.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An efficient fault simulation technique for transition faults in non-scan sequential circuits.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Comprehensive bridging fault diagnosis based on the SLAT paradigm.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

A new design-for-test technique for SRAM core-cell stability faults.
Proceedings of the Design, Automation and Test in Europe, 2009

Delay Fault Diagnosis in Sequential Circuits.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Guest Editorial.
J. Electron. Test., 2008

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.
J. Electron. Test., 2008

An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

SoC Yield Improvement: Redundant Architectures to the Rescue?
Proceedings of the 2008 IEEE International Test Conference, 2008

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs.
Proceedings of the 2008 IEEE International Test Conference, 2008

Yield Improvement, Fault-Tolerance to the Rescue?.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Using TMR Architectures for Yield Improvement.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Improving Diagnosis Resolution without Physical Information.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

SoC Symbolic Simulation: a case study on delay fault testing.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

A Design-for-Diagnosis Technique for SRAM Write Drivers.
Proceedings of the Design, Automation and Test in Europe, 2008

Power-Aware Testing and Test Strategies for Low Power Devices.
Proceedings of the Design, Automation and Test in Europe, 2008

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits.
J. Electron. Test., 2007

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

A novel scheme to reduce power supply noise for high-quality at-speed scan testing.
Proceedings of the 2007 IEEE International Test Conference, 2007

A concurrent approach for testing address decoder faults in eFlash memories.
Proceedings of the 2007 IEEE International Test Conference, 2007

DERRIC: A Tool for Unified Logic Diagnosis.
Proceedings of the 12th European Test Symposium, 2007

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.
Proceedings of the 12th European Test Symposium, 2007

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.
Proceedings of the 12th European Test Symposium, 2007

A Mixed Approach for Unified Logic Diagnosis.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Slow write driver faults in 65nm SRAM technology: analysis and March test solution.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Reducing Power Dissipation in SRAM during Test.
J. Low Power Electron., 2006

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.
J. Electron. Test., 2006

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.
J. Electron. Test., 2006

A Gated Clock Scheme for Low Power Testing of Logic Cores.
J. Electron. Test., 2006

An Overview of Failure Mechanisms in Embedded Flash Memories.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.
Proceedings of the IFIP VLSI-SoC 2006, 2006

March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Minimizing test power in SRAM through reduction of pre-charge activity.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing.
J. Low Power Electron., 2005

Welcome to the Journal of Low Power Electronics.
J. Low Power Electron., 2005

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.
J. Electron. Test., 2005

Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.
J. Electron. Test., 2005

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.
J. Electron. Test., 2005

Data Retention Fault in SRAM Memories: Analysis and Detection Procedures.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.
Proceedings of the Integrated Circuit and System Design, 2005

Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization.
Proceedings of the 10th European Test Symposium, 2005

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Power-Driven Routing-Constrained Scan Chain Design.
J. Electron. Test., 2004

March iC-: An Improved Version of March C- for ADOFs Detection.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs.
Proceedings of the 9th European Test Symposium, 2004

Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution.
Proceedings of the 9th European Test Symposium, 2004

An efficient scan tree design for test time reduction.
Proceedings of the 9th European Test Symposium, 2004

High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Design of Routing-Constrained Low Power Scan Chains.
Proceedings of the 2004 Design, 2004

Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
A Ring Architecture Strategy for BIST Test Pattern Generation.
J. Electron. Test., 2003

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Defect Analysis for Delay-Fault BIST in FPGAs.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Requirements for delay testing of look-up tables in SRAM-based FPGAs.
Proceedings of the 8th European Test Workshop, 2003

Defect-oriented dynamic fault models for embedded-SRAMs.
Proceedings of the 8th European Test Workshop, 2003

Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Hardware Generation of Random Single Input Change Test Sequences.
J. Electron. Test., 2002

High Defect Coverage with Low-Power Test Sequences in a BIST Environment.
IEEE Des. Test Comput., 2002

Survey of Low-Power Testing of VLSI Circuits.
IEEE Des. Test Comput., 2002

On Using Efficient Test Sequences for BIST.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Power Driven Chaining of Flip-Flops in Scan Architectures.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test Power: a Big Issue in Large SOC Designs.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences.
J. Electron. Test., 2001

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A Gated Clock Scheme for Low Power Scan-Based BIST.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Random Adjacent Sequences: An Efficient Solution for Logic BIST.
Proceedings of the SOC Design Methodologies, 2001

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Low Power BIST by Filtering Non-Detecting Vectors.
J. Electron. Test., 2000

Hidden Markov and Independence Models with Patterns for Sequential BIST.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Low power BIST design by hypergraph partitioning: methodology and architectures.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Low Power Testing of VLSI Circuits: Problems and Solutions.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

An adjacency-based test pattern generator for low power BIST design.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits.
J. Electron. Test., 1999

A Test Vector Inhibiting Technique for Low Energy BIST Design.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Low power BIST by filtering non-detecting vectors.
Proceedings of the 4th European Test Workshop, 1999

On calculating efficient LFSR seeds for built-in self test.
Proceedings of the 4th European Test Workshop, 1999

Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
A BIST Structure to Test Delay Faults in a Scan Environment.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
A non-iterative gate resizing algorithm for high reduction in power consumption.
Integr., 1997

An optimized BIST test pattern generator for delay testing.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

On Using Machine Learning for Logic BIST.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

A gate resizing technique for high reduction in power consumption.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996
A new test pattern generation method for delay fault testing.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Delay fault diagnosis in sequential circuits based on path tracing.
Integr., 1995

An advanced diagnostic method for delay faults in combinational faulty circuits.
J. Electron. Test., 1995

Diagnostic of path and gate delay faults in non-scan sequential circuits.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A trace-based method for delay fault diagnosis in synchronous sequential circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992
Delay-Fault Diagnosis by Critical-Path Tracing.
IEEE Des. Test Comput., 1992

A New Reliable Method for Delay-Fault Diagnosis.
Proceedings of the Fifth International Conference on VLSI Design, 1992

A Novel Approach to Delay-Fault Diagnosis.
Proceedings of the 29th Design Automation Conference, 1992


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