Alejandro Nocua

According to our database, Alejandro Nocua authored at least 11 papers between 2015 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Multilevel simulation-based co-design of next generation HPC microprocessors.

Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau

Proceedings of the 2021 International Workshop on Performance Modeling, 2021

2020

Mont-Blanc 2020: Simulation Efforts Towards Exascale High Performance Computing : Embedded Tutorial on "DDECS-2020".

Alejandro Nocua, Said Derradji, Gregory Vaumourin, Pierre-Axel Lagadec, Zoltan Menyhart

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019

A gem5 trace-driven simulator for fast architecture exploration of OpenMP workloads.

Alejandro Nocua, Florent Bruguier, Gilles Sassatelli, Abdoulaye Gamatié

Microprocess. Microsystems, 2019

2018

Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing.

David Novo, Alejandro Nocua, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli

Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

2017

A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality.

Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier

J. Low Power Electron., 2017

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization.

Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier

J. Circuits Syst. Comput., 2017

ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systems.

Alejandro Nocua, Florent Bruguier, Gilles Sassatelli, Abdoulaye Gamatié

Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

2016

A Hybrid Power Estimation Technique to improve IP power models quality.

Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

A hybrid power modeling approach to enhance high-level power models.

Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

Screening small-delay defects using inter-path correlation to reduce reliability risk.

Jose Luis Garcia-Gervacio, Alejandro Nocua, Víctor H. Champac

Microelectron. Reliab., 2015

An efficient hybrid power modeling approach for accurate gate-level power estimation.

Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier

Proceedings of the 27th International Conference on Microelectronics, 2015