Dale E. Hocevar

According to our database1, Dale E. Hocevar authored at least 19 papers between 1982 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2006
A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2003
LDPC code construction with flexible hardware implementation.
Proceedings of IEEE International Conference on Communications, 2003

Efficient encoding for a family of quasi-cyclic LDPC codes.
Proceedings of the Global Telecommunications Conference, 2003

A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder.
Proceedings of the Global Telecommunications Conference, 2003

2002
600 MHz DSP for baseband processing in 3G base stations.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
Improving performance of a space-time turbo code in a Rayleigh fading channel.
Proceedings of the 54th IEEE Vehicular Technology Conference, 2001

Space-time codes with bit interleaving.
Proceedings of the Global Telecommunications Conference, 2001

1998
Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1991
Direct circuit simulation algorithms for parallel processing [VLSI].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1990
A Usable Circuit Optimizer for Designers.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
New implicit integration method for efficient latency exploitation in circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988
Parametric yield optimization for MOS circuit blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
SPIDER -- A CAD System for Modeling VLSI Metallization Patterns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1986
An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

1985
Transient Sensitivity Computation for MOSFET Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

1984
An Extrapolated Yield Approximation Technique for Use in Yield Maximization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1983
A Study of Variance Reduction Techniques for Estimating Circuit Yields.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

1982
Automatic Tuning Algorithms and Statistical Circuit Design
PhD thesis, 1982


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