Yanni Chen

Orcid: 0000-0002-0436-6937

According to our database1, Yanni Chen authored at least 24 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Continuous and discrete local hidden variable theories are equivalent.
Inf. Sci., November, 2023

A Bi-level gaming programming for regional integrated energy system considering the users' reliability incentive.
Reliab. Eng. Syst. Saf., 2023

Achieving Timestamp Prediction While Recognizing with Non-Autoregressive End-to-End ASR Model.
CoRR, 2023

A Review of State-of-the-arts Sensing Techniques for the Ultra-early Screening of Cerebral Palsy.
Proceedings of the IEEE International Conference on Real-time Computing and Robotics, 2023

2021
Effects of Muscle Fatigue and Recovery on Complexity of Surface Electromyography of Biceps Brachii.
Entropy, 2021

A Resilience Enhancement Model for Complex Distribution Network Coupling with Human Resources and Traffic Network.
Complex., 2021

Using DeepGCN to identify the autism spectrum disorder from multi-site resting-state data.
Biomed. Signal Process. Control., 2021

2020
Effect of Different Local Vibration Frequencies on the Multiscale Regularity of Plantar Skin Blood Flow.
Entropy, 2020

Abnormal Brain Regions in Two-Group Cross-Location Dynamics Model of Autism.
IEEE Access, 2020

Risk Assessment of Cyber Attacks on Power Grids Considering the Characteristics of Attack Behaviors.
IEEE Access, 2020

2017
A general Beurling-Helson-Lowdenslager theorem on the disk.
Adv. Appl. Math., 2017

2013
Signal Flow Graphs and Data Flow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2013

2010
Signal Flow Graphs and Data Flow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2010

2006
A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2005
On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes.
J. VLSI Signal Process., 2005

2004
Small area parallel Chien search architectures for long BCH codes.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Overlapped message passing for quasi-cyclic low-density parity check codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Area efficient decoding of quasi-cyclic low density parity check codes.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Area efficient parallel decoder architecture for long BCH codes.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
Low-Complexity Decoding of Block Turbo-Coded System with Antenna Diversity.
EURASIP J. Adv. Signal Process., 2003

High throughput overlapped message passing for low density parity check codes.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder.
Proceedings of the Global Telecommunications Conference, 2003

2002
A very low complexity soft decoding of space-time block codes.
Proceedings of the IEEE International Conference on Acoustics, 2002

2001
A very low complexity block turbo decoder composed of extended Hamming codes.
Proceedings of the Global Telecommunications Conference, 2001


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