Dan Lei Yan

According to our database1, Dan Lei Yan authored at least 9 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 35mW, 2.32dB NF, 1.1° Phase Error, 18-21.2GHz Beamforming Receiver IC for Satcom on the Move (SOTM) Phased Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

2017
A -121dBm sensitivity, 2μJ/bit Rx, 8.8μJ/bit Tx, narrowband transceiver for ARIB STD and IoT.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Digital Compensation Method for the Path Delay Mismatches in GRO-TDC.
J. Circuits Syst. Comput., 2016

A low-power digital design of all digital PLL for 2.4G wireless communication applications.
Proceedings of the International Symposium on Integrated Circuits, 2016

A 5.1Gb/s 60.3fJ/bit/mm PVT tolerant NoC transceiver.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2014
A 400MHz low power fractional-N synthesizer with GFSK/GMSK modulation in 0.13μm CMOS.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A fully integrated 166-GHz frequency synthesizer in 0.13-μm SiGe BiCMOS for D-band applications.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2008
A Universal UHF RFID Reader IC in 0.18-µm CMOS Technology.
IEEE J. Solid State Circuits, 2008

2007
A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007


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