Jun Zhou

Affiliations:
  • University of Electronic Science and Technology of China, Smart ICs and Systems Research Group, Chengdu, China
  • A*STAR, Institute of Microelectronics, Singapore (former)
  • Newcastle University, Newcastle upon Tyne, UK (PhD 2008)


According to our database1, Jun Zhou authored at least 54 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

On csauthors.net:

Bibliography

2022
ULECGNet: An Ultra-Lightweight End-to-End ECG Classification Neural Network.
IEEE J. Biomed. Health Informatics, 2022

<i>LCSED</i>: A low complexity CNN based SED model for IoT devices.
Neurocomputing, 2022

2021
A Fast and Energy-Efficient SNN Processor With Adaptive Clock/Event-Driven Computation Scheme and Online Learning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Magnetic Resistance Sensory System for the Quantitative Measurement of Morphine.
IEEE Trans. Biomed. Circuits Syst., 2021

A Lightweight Pedestrian Detection Engine with Two-Stage Low-Complexity Detection Network and Adaptive Region Focusing Technique.
Sensors, 2021

Keyword spotting techniques to improve the recognition accuracy of user-defined keywords.
Neural Networks, 2021

A Weight Importance Analysis Technique for Area- and Power-Efficient Binary Weight Neural Network Processor Design.
Cogn. Comput., 2021

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective.
Sci. China Inf. Sci., 2021

A Review of Convolutional Neural Networks Hardware Accelerators for AIoT Edge Computing.
Proceedings of the International Conference on UK-China Emerging Technologies, 2021

4.5 BioAIP: A Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Intelligent Health Monitoring.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A Survey on Feature Point Extraction Techniques.
Proceedings of the 18th International SoC Design Conference, 2021

Trend of Emerging Non-Volatile Memory for AI Processor.
Proceedings of the 18th International SoC Design Conference, 2021

Energy-Efficient Spin-Orbit Torque MRAM Operations for Neural Network Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

RAODAT: An Energy-Efficient Reconfigurable AI-based Object Detection and Tracking Processor with Online Learning.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
TSE-CNN: A Two-Stage End-to-End CNN for Human Activity Recognition.
IEEE J. Biomed. Health Informatics, 2020

Guest Editorial: Special Section on AI-Based Biomedical Circuits and Systems.
IEEE Trans. Biomed. Circuits Syst., 2020

A Review of Algorithm & Hardware Design for AI-Based Biomedical Applications.
IEEE Trans. Biomed. Circuits Syst., 2020

A Biological Retina Inspired Tone Mapping Processor for High-Speed and Energy-Efficient Image Enhancement.
Sensors, 2020

Corrigendum to"Approximate error detection-correction for efficient adaptive voltage Over-Scaling"[Integration 63 (2018) 220-231].
Integr., 2020

Adaptable Map Matching Using PF-net for Pedestrian Indoor Localization.
IEEE Commun. Lett., 2020

Scalability Analysis and Modeling of XPoint-based MRAM.
Proceedings of the International SoC Design Conference, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Energy-Efficient Intelligent ECG Monitoring for Wearable Devices.
IEEE Trans. Biomed. Circuits Syst., 2019

A High Throughput and Energy-Efficient Retina-Inspired Tone Mapping Processor.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
A 1-V to 0.29-V sub-100-pJ/operation ultra-low power fast-convergence CORDIC processor in 0.18-μm CMOS.
Microelectron. J., 2018

Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling.
Integr., 2018

RNS-Based Embedding Scheme for Data Hiding in Digital Images.
Proceedings of the 17th IEEE International Conference On Trust, 2018

A FPGA-based RO PUF with LUT-Based Self-Compare Structure and Adaptive Counter Time Period Tuning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
An Ultra-Low Power Turning Angle Based Biomedical Signal Compression Engine with Adaptive Threshold Tuning.
Sensors, 2017

A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance.
Microelectron. J., 2017

Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

Near-threshold processor design techniques for power-constrained computing devices.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 151-nW Adaptive Delta-Sampling ADC for Ultra-Low Power Sensing Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 12.77-MHz 31 ppm/°C On-Chip RC Relaxation Oscillator With Digital Compensation Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 65-nm 0.35-V 7.1-μW memory-less adaptive PCG processor for wearable long-term cardiac monitoring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Near-Threshold Energy- and Area-Efficient Reconfigurable DWPT/DWT Processor for Healthcare-Monitoring Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Fast and energy-efficient low-voltage level shifters.
Microelectron. J., 2015

SRAM devices and circuits optimization toward energy efficiency in multi-V<sub>th</sub> CMOS.
Microelectron. J., 2015

A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression.
Proceedings of the ESSCIRC Conference 2015, 2015

A 12.77-MHz on-chip relaxation oscillator with digital compensation for loop delay variation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

Opportunities and challenges: Ultra-low voltage digital IC design techniques.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring.
IEEE J. Solid State Circuits, 2014

30.7 A 60Mb/s wideband BCC transceiver with 150pJ/b RX and 31pJ/b TX for emerging wearable applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

An area- and power-efficient FIFO with error-reduced data compression for image/video processing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A sub-threshold to super-threshold Level Conversion Flip Flop for sub/near-threshold dual-supply operation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2011
A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library.
Proceedings of the 48th Design Automation Conference, 2011

Exploring AMBA AXI on-Chip interconnection for TSV-based 3D SoCs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011


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