Daniel L. Ostapko

According to our database1, Daniel L. Ostapko authored at least 17 papers between 1968 and 2005.

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Awards

IEEE Fellow

IEEE Fellow 1989, "For contributions to design automation, fault-tolerant computing , and to programmable logic arrays.".

Timeline

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Bibliography

2005
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004
Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis.
Proceedings of the Integrated Circuit and System Design, 2004

2001
On the Signal Bounding Problem in Timing Analysis.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

1984
A Mapping and Memory Chip Hardware which Provides Symmetric Reading/Writing of Horizontal and Vertical Lines.
IBM J. Res. Dev., 1984

1982
Interactive design language: A unified approach to hardware simulation, synthesis and documentation.
Proceedings of the 19th Design Automation Conference, 1982

1981
A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks.
IEEE Trans. Computers, 1981

1979
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's).
IEEE Trans. Computers, 1979

1975
Codes for Self-Clocking, AC-Coupled Transmission: Aspects of Synthesis and Analysis.
IBM J. Res. Dev., 1975

1974
On deriving a relation between circuits and input/output by analyzing an equivalent program.
ACM SIGPLAN Notices, 1974

Generating Test Examples for Heuristic Boolean Minimization.
IBM J. Res. Dev., 1974

MINI: A Heuristic Approach for Logic Minimization.
IBM J. Res. Dev., 1974

Analysis of algorithms implemented in software and hardware.
Proceedings of the 1974 ACM Annual Conference, 1974

1972
On Complementation of Boolean Functions.
IEEE Trans. Computers, 1972

1971
Minimum test patterns for residue networks.
Proceedings of the 8th Design Automation Workshop, 1971

1970
Realization of an Arbitrary Switching Function with a Two-Level Network of Threshold and Parity Elements.
IEEE Trans. Computers, 1970

Optimum test patterns for parity networks.
Proceedings of the American Federation of Information Processing Societies: Proceedings of the AFIPS '70 Fall Joint Computer Conference, 1970

1968
Realization of a Class of Switching Functions by Threshold-Logic Networks.
IEEE Trans. Computers, 1968


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