Martin S. Schmookler

According to our database1, Martin S. Schmookler authored at least 13 papers between 1968 and 2007.

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Bibliography

2007
P6 Binary Floating-Point Unit.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2005
FPU Implementations with Denormalized Numbers.
IEEE Trans. Computers, 2005

Pain versus Gain in the Hardware Design of FPUs and Supercomputers.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2003
Hardware Implementations of Denormalized Numbers.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2001
Leading Zero Anticipation and Detection-A Comparison of Methods.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

1999
A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

Series Approximation Methods for Divide and Square Root in the Power3(TM) Processor.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1995
Avoiding Unknown States When Scanning Mutually Exclusive Latches.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1971
High Speed Decimal Addition.
IEEE Trans. Computers, 1971

Minimum test patterns for residue networks.
Proceedings of the 8th Design Automation Workshop, 1971

1969
On Mod-2 Sums of Products.
IEEE Trans. Computers, 1969

1968
High-Speed Binary-to-Decimal Conversion.
IEEE Trans. Computers, 1968

A Random-Walk Model of a Queue Storage Problem.
IEEE Trans. Computers, 1968


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