Daniel Thiele

According to our database1, Daniel Thiele authored at least 15 papers between 2012 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Networked Real-Time Embedded Systems.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

A system-level FPGA design methodology for video applications with weakly-programmable hardware components.
J. Real-Time Image Processing, 2017

2016
Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks.
Real-Time Systems, 2016

Formal worst-case performance analysis of time-sensitive Ethernet with frame preemption.
Proceedings of the 21st IEEE International Conference on Emerging Technologies and Factory Automation, 2016

Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaper.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Formal analysis based evaluation of software defined networking for time-sensitive Ethernet.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Towards fail-operational ethernet based in-vehicle networks.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Formal worst-case timing analysis of Ethernet TSN's time-aware and peristaltic shapers.
Proceedings of the 2015 IEEE Vehicular Networking Conference, 2015

Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Formal timing analysis of automatic repeat request for switched real-time networks.
Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems, 2014

Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Improving formal timing analysis of switched ethernet by exploiting traffic stream correlations.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013
Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012
Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Optimizing performance analysis for synchronous dataflow graphs with shared resources.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012


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