Jonas Diemer

According to our database1, Jonas Diemer authored at least 18 papers between 2009 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Networked Real-Time Embedded Systems.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Formal worst-case timing analysis of Ethernet TSN's time-aware and peristaltic shapers.
Proceedings of the 2015 IEEE Vehicular Networking Conference, 2015

FMEA-based analysis of a Network-on-Chip for mixed-critical systems.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Failure analysis of a network-on-chip for real-time mixed-critical systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

IDAMC: A NoC for mixed criticality systems.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

Safe Virtual Interrupts Leveraging Distributed Shared Resources and Core-to-Core Communication on Many-Core Platforms.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Power Monitoring for Mixed-Criticality on a Many-Core Platform.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Exploring the worst-case timing of Ethernet AVB for industrial applications.
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012

IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality.
Proceedings of the 14th International IEEE Symposium on High-Assurance Systems Engineering, 2012

Mastering MPSoCs for Mixed-critical Applications.
IPSJ Trans. System LSI Design Methodology, 2011

Real-time communication analysis for networks with two-stage arbitration.
Proceedings of the 11th International Conference on Embedded Software, 2011

Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks.
Proceedings of the NOCS 2010, 2010

A Polynomial-Time Algorithm for Computing Response Time Bounds in Static Priority Scheduling Employing Multi-linear Workload Bounds.
Proceedings of the 22nd Euromicro Conference on Real-Time Systems, 2010

Efficient throughput-guarantees for latency-sensitive networks-on-chip.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

A link arbitration scheme for quality of service in a latency-optimized network-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2009