Daniele Mangano

According to our database1, Daniele Mangano authored at least 7 papers between 2005 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2010
Enabling dynamic and programmable QoS in SoCs.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

2007
Relieving physical issues in new NoC-based SoCs.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Skew Insensitive Physical Links for Network on Chip.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

GALS networks on chip: a new solution for asynchronous delay-insensitive links.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005
A cache design for high performance embedded systems.
J. Embedded Computing, 2005

A NUCA Model for Embedded Systems Cache Design.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005


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