Riccardo Locatelli

According to our database1, Riccardo Locatelli authored at least 26 papers between 2002 and 2022.

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Bibliography

2022
Design and Implementation on FPGA of a HW Accelerator for Post-Quantum RLWE Polynomial Operations.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

2014
Design of an NoC Interface Macrocell with Hardware Support of Advanced Networking Functionalities.
IEEE Trans. Computers, 2014

Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead.
IEEE Trans. Computers, 2014

2011
Coverage-Driven Verification of HDL IP Cores - Case Study of a Router for Network-on-Chip Communication in Embedded Systems.
Proceedings of the Solutions on Embedded Systems, 2011

Efficient routing implementation in complex systems-on-chip.
Proceedings of the NOCS 2011, 2011

EEEP: an <i>extreme end</i> to <i>end</i> flow control <i>protocol</i> for SDRAM access through networks on chip.
Proceedings of the Fifth International Workshop on Interconnection Network Architecture, 2011

2010
The Connection-Then-Credit Flow Control Protocol for Heterogeneous Multicore Systems-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Error resilience of intra-die and inter-die communication with 3D spidergon STNoC.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A reusable coverage-driven verification environment for Network-on-Chip communication in embedded system platforms.
Proceedings of the Seventh Workshop on Intelligent solutions in Embedded Systems, 2009

CTC: An end-to-end flow control protocol for multi-core systems-on-chip.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

2008
Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip.
IEEE Trans. Computers, 2008

An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC.
IEEE Des. Test Comput., 2008

LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
A topology design customization approach for STNoC.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Application-Specific Topology Design Customization for STNoC.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

NoC Topologies Exploration based on Mapping and Simulation Models.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Mapping and Topology Customization Approaches for Application-Specific STNoC Designs.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Skew Insensitive Physical Links for Network on Chip.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

2004
Design methodologies and advanced architectures for system on chip platforms: focus on communication.
PhD thesis, 2004

OCCN: a NoC modeling framework for design exploration.
J. Syst. Archit., 2004

Spidergon: a novel on-chip communication network.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

VLSI Design of a Digital RFI Cancellation Scheme for VDSL Transceivers.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003
RFI Cancellation in DMT VDSL: A Digital Frequency Domain Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Permanent Scatterers: precision assessment and multi-platform analysis.
Proceedings of the 2003 IEEE International Geoscience and Remote Sensing Symposium, 2003

2002
Ground deformation monitoring exploiting SAR permanent scatterers.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2002


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