Marcello Coppola

Orcid: 0000-0003-0414-9411

According to our database1, Marcello Coppola authored at least 55 papers between 2003 and 2022.

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Bibliography

2022
Studio4Education: Model Driven Graphical Programming of IoT applications for Education.
Proceedings of the IECON 2022, 2022

Poster: Secure Multi-tenant Provisioning of IoT Devices by Combining On-chip Cortex-M TrustZone with Secure Element.
Proceedings of the 2022 International Conference on Embedded Wireless Systems and Networks, 2022

2021
Secure Asset Tracking in Manufacturing through Employing IOTA Distributed Ledger Technology.
Proceedings of the 21st IEEE/ACM International Symposium on Cluster, 2021

2020
Efficient Job Offloading in Heterogeneous Systems Through Hardware-Assisted Packet-Based Dispatching and User-Level Runtime Infrastructure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Towards holistic secure networking in connected vehicles through securing CAN-bus communication and firmware-over-the-air updating.
J. Syst. Archit., 2020

2019
TrustNet: Ensuring Normal-world and Trusted-world CAN-bus Networking.
Proceedings of the 2019 IEEE International Conference on Communications, 2019

2018
Hardware-Assisted Security in Electronic Control Units: Secure Automotive Communications by Utilizing One-Time-Programmable Network on Chip and Firewalls.
IEEE Micro, 2018

Enabling Efficient Job Dispatching in Accelerator-Extended Heterogeneous Systems with Unified Address Space.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

2017
Soft real-time smartphone ECG processing.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

2016
Efficient communication in heterogeneous SoCs with unified address space.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Address interleaving for low-cost NoCs.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

ECOSCALE: Reconfigurable computing and runtime system for future exascale systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

On-chip networks for mixed-criticality systems.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Security in MPSoCs: A NoC Firewall and an Evaluation Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

High-level security services based on a hardware NoC Firewall module.
Proceedings of the 12th International Workshop on Intelligent Solutions in Embedded Systems, 2015

Security Enhancements for building saturation-free, low-power NoC-based MPSoCs.
Proceedings of the 2015 IEEE Conference on Communications and Network Security, 2015

2014
Design of an NoC Interface Macrocell with Hardware Support of Advanced Networking Functionalities.
IEEE Trans. Computers, 2014

Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead.
IEEE Trans. Computers, 2014

Security Effectiveness and a Hardware Firewall for MPSoCs.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
From embedded multi-core SoCs to scale-out processors.
Proceedings of the Design, Automation and Test in Europe, 2013

TRESCCA - Trustworthy Embedded Systems for Secure Cloud Computing.
Proceedings of the 2013 International Conference on Availability, Reliability and Security, 2013

2012
Many-core platform with NoC interconnect for low cost and energy sustainable cloud server-on-chip.
Proceedings of the Sustainable Internet and ICT for Sustainability, 2012

Accurate on-chip router area modeling with Kriging methodology.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Towards Full Virtualization of Heterogeneous NoC-based Multicore Embedded Architectures.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

How Green IS Your Cloud? - A 64-b ARM-based Heterogeneous Computing Platform with NoC Interconnect for Server-on-chip Energy-efficient Cloud Computing.
Proceedings of the CLOSER 2012 - Proceedings of the 2nd International Conference on Cloud Computing and Services Science, Porto, Portugal, 18, 2012

2011
Coverage-Driven Verification of HDL IP Cores - Case Study of a Router for Network-on-Chip Communication in Embedded Systems.
Proceedings of the Solutions on Embedded Systems, 2011

Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects.
Microprocess. Microsystems, 2011

Dynamic resource management in modern multicore SoCs by exposing NoC services.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Spidergon STNoC design flow.
Proceedings of the NOCS 2011, 2011

Efficient routing implementation in complex systems-on-chip.
Proceedings of the NOCS 2011, 2011

EEEP: an <i>extreme end</i> to <i>end</i> flow control <i>protocol</i> for SDRAM access through networks on chip.
Proceedings of the Fifth International Workshop on Interconnection Network Architecture, 2011

Power-Aware Multicore SoC and NoC Design.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
3D self testing with Spidergon STNoC.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Off-Chip SDRAM Access Through Spidergon STNoC.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Small Worlds: The Dynamics of NoCs in Tomorrow SoC Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Spidergon STNoC: The technology that adds value to your System.
Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010

2009
A reusable coverage-driven verification environment for Network-on-Chip communication in embedded system platforms.
Proceedings of the Seventh Workshop on Intelligent solutions in Embedded Systems, 2009

Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008
Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip.
IEEE Trans. Computers, 2008

An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC.
IEEE Des. Test Comput., 2008

LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
A topology design customization approach for STNoC.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Application-Specific Topology Design Customization for STNoC.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

NoC Topologies Exploration based on Mapping and Simulation Models.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Mapping and Topology Customization Approaches for Application-Specific STNoC Designs.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Skew Insensitive Physical Links for Network on Chip.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2005
An Open Platform for Developing Multiprocessor SoCs.
Computer, 2005

2004
OCCN: a NoC modeling framework for design exploration.
J. Syst. Archit., 2004

Spidergon: a novel on-chip communication network.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

OCCN: A Network-On-Chip Modeling and Simulation Framework.
Proceedings of the 2004 Design, 2004

2003
High Level Modeling and Simulation of a VDSL Modem in SystemC 2.0 - IPsim.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

IPSIM: SystemC 3.0 Enhancements for Communication Refinement.
Proceedings of the 2003 Design, 2003

Software for Multiprocessor Networks on Chip.
Proceedings of the Networks on Chip, 2003


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